Microcomputer Systems 1

Microcomputer Systems 1
Digital Systems: Hardware Organization and Design 9/19/2018 Microcomputer Systems 1 Interaction of ADSP-BF533 Ez-Kit Lite with the outside world LAB1 Example Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design
9/19/2018 BF533 EZ-Kit Lite The EZ-KIT Lite provides four (4) push buttons and six (6) LEDs for general-purpose IO. 6 LEDs The six LEDs, labeled LED4 through LED9, are accessed via some of the general-purpose IO pins of the flash memory interface. 4 SW push-button switches The four general-purpose push button switches are labeled SW4 through SW7. A status of each individual button can be read through programmable flag (PF) inputs: PF8 through PF11. A PF reads 1 when a corresponding switch is being pressed-on. When the switch is released, the PF reads 0. A connection between the push button and PF input is established through the SW9 DIP switch. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 BF533 EZ-Kit Lite 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SW9 Switch For more information see “ADSP-BF533 EZ-KIT Lite Evaluation System Manual”: ADSP_BF533_EZ_KIT_Lite_Manual_Rev_3.0.pdf 19 September 2018 Veton Këpuska

Push Button Enable Switch (SW9)
Positions: 1 through 4 : disconnect the drivers associated with the push buttons from the PF pins of the processor. 5 and 6 : are used to connect the transmit and receive frame syncs and clocks of SPORT0. This is important when the AD1836 video decoder and the processor are communicating in I2S mode. Table 2-6 shows which PF is driven when the switch is in the default (ON) position. 19 September 2018 Veton Këpuska

BF533 EZ-Kit Lite Circuit Schematics
19 September 2018 Veton Këpuska

9/19/2018 Lab 1 Details Source code directory contains an example ADSP-BF533 project that shows how Programmable Flag pins (FIO), Interrupts, and Timer can be configured in “C”. It also demonstrates the access to the LEDs on the EZ-KIT Lite, which are connected to the on-board Flash. Files contained in this directory: BF533 Flags C.dpj VisualDSP++ project file main.c C file containing the main program and variable declaration Initialisation.c C file containing all initialization routines ISRs.c C file containing the interrupt service routines for Timer and FIO BF533 Flags.h C header file containing prototypes and macros readme.txt this project description file 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Lab 1: Functional Description
Digital Systems: Hardware Organization and Design 9/19/2018 Lab 1: Functional Description This example demonstrates the initialization of the External Bus Interface Unit - EBIU (asynchronous access), Timer 0, FIO pins, Interrupts and the on-board Flash, which allows access to the six LEDs on the EZ-KIT. The program simply turns on one LED and rotates the pattern left or right, depending on the state of an internal flag. The switch connected to PF8 (SW4) can be used to toggle the state of this flag, which results in a change of direction of the moving light. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Lab 1: Implementation Description
Digital Systems: Hardware Organization and Design 9/19/2018 Lab 1: Implementation Description The main file calls: FIO setup Timer setup EBIU setup Flash setup Interrupt configuration Endless loop waiting for Timer interrupt or Flag interrupt 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Lab 1. Code Walk Through #include "BF533 Flags.h" #include "ccblkfn.h" #include "sysreg.h" // // // Variables // // flag indicating direction of moving light (toggled in FlagA ISR) short sLight_Move_Direction = 0; // Function: main // void main(void) { sysreg_write(reg_SYSCFG, 0x32); //Initialize System Configuration Register Init_Flags(); Init_Timers(); Init_EBIU(); Init_Flash(); Init_Interrupts(); while(1); } 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 BF533 Flags.h #ifndef __BF533_FLAGS_DEFINED #define __BF533_FLAGS_DEFINED // // // Header files // #include <sys\exception.h> #include <cdefBF533.h> // Symbolic constants // // addresses for Port B in Flash A #define pFlashA_PortB_Dir (volatile unsigned char *)0x #define pFlashA_PortB_Data (volatile unsigned char *)0x // Global variables // extern short sLight_Move_Direction; // Prototypes // // in file Initialization.c void Init_Flags(void); void Init_Timers(void); void Init_EBIU(void); void Init_Flash(void); void Init_Interrupts(void); // in file ISRs.c EX_INTERRUPT_HANDLER(Timer0_ISR); EX_INTERRUPT_HANDLER(FlagA_ISR); #endif //__BF533_FLAGS_DEFINED See Table 1-5. Flash A Configuration Registers for Ports A and B in slide 14 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Lab 1: Note Make sure that switch SW9 pin1 is turned on (connects switch SW7 to pin PF8) 1 2 3 4 5 6 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 LED Interface Architecture of a Respresentative 32 Bit Processor

How to “configure” the flash memory to control the LEDs
Digital Systems: Hardware Organization and Design 9/19/2018 How to “configure” the flash memory to control the LEDs Parallel interfaces present on the FLASH memory chips 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Flash General-Purpose IO
Digital Systems: Hardware Organization and Design 9/19/2018 Flash General-Purpose IO General-purpose IO signals are controlled by means of setting appropriate registers of the flash A or flash B. These registers are mapped into the processor’s address space, as shown in the Table below (ADSP-BF533 EZ-KIT Lite Evaluation System Manual – Flash Memory) 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Flash General-Purpose IO
Digital Systems: Hardware Organization and Design 9/19/2018 Flash General-Purpose IO Flash device IO pins are arranged as 8-bit ports labeled A through G. There is a set of 8-bit registers associated with each port. These registers are used for: Direction, Data In, and Data Out. Note that the Direction and Data Out registers are cleared to all zeros at power-up or hardware reset. The Direction register controls IO pins direction. This is a 8-bit read-write register. When a bit is 0, a corresponding pin functions as an input. When the bit is 1, a corresponding pin is an output. The Data In register allows reading the status of port’s pins. This is a 8-bit read-only register. The Data Out register allows clearing an output pin to 0 or setting it to 1. This is a 8-bit read-write register. The ADSP-BF533 EZ-KIT Lite board employs only flash A and flash B ports A and B. Table 1-5 and Table 1-6 provide configuration register addresses for flash A and flash B, respectively (only ports A and B are listed in the next slide). The following bits connect to the expansion board connector. Flash A: port A bits 7 and 6, as well as port B bits 7 and 6 Flash B: port A bits 7–0 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Flash A & B Configuration Registers for Ports A and B.
Digital Systems: Hardware Organization and Design 9/19/2018 Flash A & B Configuration Registers for Ports A and B. Table 1-5. Flash A Configuration Registers for Ports A and B Table 1-6. Flash B Configuration Registers for Ports A and B Register Name Port A Address Port B Address Data In (read-only) 0x 0x Data Out (read-write) 0x 0x Direction (read-write) 0x 0x Register Name Port A Address Port B Address Data In (read-only) 0x202E 0000 0x202E 0001 Data Out (read-write) 0x202E 0004 0x202E 0005 Direction (read-write) 0x202E 0006 0x202E 0007 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

IO Assignments for Port A and Port B
Digital Systems: Hardware Organization and Design 9/19/2018 IO Assignments for Port A and Port B Table 1-7 Flash A Port A Controls. PPI – Parallel Peripheral Interface & Associated Configuration Registers. Bit Number User IO Bit Value 7 Not defined Any 6 5 PPI clock select bit 1 00=local OSC (27MHz) 4 PPI clock select bit 0 01=video decoder pixel clock 1x=expansion board PPI clock 3 Video decoder reset 0=reset ON; 1=reset OFF 2 Video encoder reset 1 Reserved Codec reset 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

IO Assignments for Port A and Port B
Digital Systems: Hardware Organization and Design 9/19/2018 IO Assignments for Port A and Port B Table 1-8 Flash A Port B Controls. Bit Number User IO Bit Value 7 Not used Any 6 5 LED9 0=LED OFF; 1=LED ON 4 LED8 3 LED7 2 LED6 1 LED5 LED4 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 User LEDs (LED4-9) Six LEDs connect to six general-purpose IO pins of the flash memory (U5). The LEDs are active high and are lit by writing a 1 to the correct memory address in the flash memory. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

BF533 Interface to PFI/PFs
Digital Systems: Hardware Organization and Design 9/19/2018 BF533 Interface to PFI/PFs PFI/PFs 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 FIO Setup FIO setup Timer setup EBIU setup Flash setup Interrupt configuration Endless loop waiting for Timer interrupt or Flag interrupt Architecture of a Respresentative 32 Bit Processor

9/19/2018 Initialization.c #include "BF533 Flags.h" // // // Function: Init_Flags // // // // Parameters: None // // // // Return: None // // Description: This function configures PF8 as input for edge sensitive // // interrupt generation // // The switch connected to PF8 (SW4) can be used to change the // // direction of the moving light // void Init_Flags(void) { *pFIO_INEN = 0x0100; *pFIO_DIR = 0x0000; *pFIO_EDGE = 0x0100; *pFIO_MASKA_D = 0x0100; } This value programs PF8 pin. See BF533 HRM or slide 25for additional information. This reset value makes all pins as inputs. See BF533 HRM or slide 26for additional information This value sets PF8 pin to be EDGE sensitive See BF533 HRM or slide 28for additional information This value enables PF8 pin to accepts interrupts. See BF533 HRM or slide 30 for additional information 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Programmable Flags PFI/PFs
Digital Systems: Hardware Organization and Design 9/19/2018 Programmable Flags PFI/PFs The processor supports 16 bidirectional programmable flags (PFx) or general-purpose I/O pins, PF[15:0]. Each pin can be individually configured as either an input or an output by using the Flag Direction register (FIO_DIR). When configured as output: the Flag Data register (FIO_FLAG_D) can be directly written to specify the state of all PFx pins. the state written to the Flag Set (FIO_FLAG_S), Flag Clear (FIO_FLAG_C), and Flag Toggle (FIO_FLAG_T) registers determines the state driven by the output PFx pin. Regardless of how the pins are configured, as an input or an output, reading any of these registers: FIO_FLAG_D, FIO_FLAG_S, FIO_FLAG_C, or FIO_FLAG_T returns the state of each pin. They can be enabled via bits in Flag Input Enable register (FIO_INEN) Input buffer associated with the PF flags is disabled by default. The Flag Input Enable register (FIO_INEN) is used to enable them. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Flag Input Enable Register
Digital Systems: Hardware Organization and Design 9/19/2018 Flag Input Enable Register ADSP-BF533 Blackfin Processor Hardware Reference 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 FIO_DIR Register Each pin, PF[15:0], can be individually configured as either an input or an output by using the Flag Direction register (FIO_DIR) The Flag Direction register (FIO_DIR) is a read-write register. Each bit position corresponds to a PFx pin. A logic 1 configures a PFx pin as an output, driving the state contained in the FIO_FLAG_D register. A logic 0 configures a PFx pin as an input. The reset value of this register is 0x0000, making all PF pins inputs upon reset. ⓘ Note when using the PFx pin as an input, the corresponding bit should also be set in the Flag Input Enable register. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Programming PFx to generate an interrupt
Digital Systems: Hardware Organization and Design 9/19/2018 Programming PFx to generate an interrupt Each PFx pin can be configured to generate an interrupt. When a PFx pin is configured as an input, an interrupt can be generated according to the state of the pin, either high or low an edge transition (low to high or high to low), or on both edge transitions (low to high and high to low). Input sensitivity is defined on a per-bit basis by the Flag Polarity register (FIO_POLAR), the Flag Interrupt Sensitivity register (FIO_EDGE) and The Flag Set on Both Edges register (FIO_BOTH). Input polarity is defined on a per-bit basis by the Flag Polarity register. When the PFx inputs are enabled and a PFx pin is configured as an output, enabling interrupts for the pin allows an interrupt to be generated by setting the PFx pin. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

FIO_EDGE: Flag Interrupt Sensitivity Register
Digital Systems: Hardware Organization and Design 9/19/2018 FIO_EDGE: Flag Interrupt Sensitivity Register 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

FIO_MASKx_D, FIO_MASKx_C, FIO_MASKx_S, FIO_MASKx_T,
Digital Systems: Hardware Organization and Design 9/19/2018 FIO_MASKx_D, FIO_MASKx_C, FIO_MASKx_S, FIO_MASKx_T, Both Flag Interrupt A and Flag Interrupt B are supported by a set of four dedicated registers: Flag Mask Interrupt Data register Flag Mask Interrupt Set register Flag Mask Interrupt Clear register Flag Interrupt Toggle register The Flag Mask Interrupt registers: FIO_MASKA_D, FIO_MASKA_S, FIO_MASKA_C, FIO_MASKA_T, and FIO_MASKB_D, FIO_MASKB_S, FIO_MASKB_C, FIO_MASKB_T are implemented as complementary pairs of: Data “D”, write-1-to-set “S”, write-1-to-clear “C”, and write-1-to-toggle “T” registers. This implementation provides the ability to: enable or disable a PFx pin to act as a processor interrupt without requiring read-modify-write accesses—or to directly specify the mask value with the data register. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

FIO_MASKA_D Register to Enable Interrupt
Digital Systems: Hardware Organization and Design 9/19/2018 FIO_MASKA_D Register to Enable Interrupt 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Timer Set Up FIO setup Timer setup EBIU setup Flash setup Interrupt configuration Endless loop waiting for Timer interrupt or Flag interrupt Architecture of a Respresentative 32 Bit Processor

9/19/2018 Timer Setup The processor features three identical 32-bit general-purpose timers, a core timer, and a watchdog timer. The general-purpose timers can be individually configured in any of three modes: Pulse Width Modulation (PWM_OUT) mode Pulse Width Count and Capture (WDTH_CAP) mode External Event (EXT_CLK) mode The core timer is available to generate periodic interrupts for a variety of system timing functions. The watchdog timer can be used to implement a software watchdog function. A software watchdog can improve system availability by generating an event to the Blackfin processor core if the timer expires before being updated by software. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Initialization.c // // // Function: Init_Timers // // // // Parameters: None // // Return: None // // Description: This function initialises Timer0 for PWM mode // // It is used as reference for the 'shift-clock' // void Init_Timers(void) { *pTIMER0_CONFIG = 0x0019; *pTIMER0_PERIOD = 0x ; *pTIMER0_WIDTH = 0x ; *pTIMER_ENABLE = 0x0001; } 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

General-Purpose Timer
Digital Systems: Hardware Organization and Design 9/19/2018 General-Purpose Timer Each general-purpose timer has one dedicated bidirectional chip pin, TMRx. This pin functions as: an output pin in the PWM_OUT mode and as an input pin in the WDTH_CAP and EXT_CLK modes. To provide these functions, each timer has (4) four 32 bit registers. Timer Configuration (TIMERx_CONFIG) registers Timer Counter (TIMERx_COUNTER) registers Timer Period (TIMERx_PERIOD) registers Timer Pulse Width (TIMERx_WIDTH) registers 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Timer Block Diagram When clocked internally, the clock source is the processor’s peripheral clock (SCLK). Assuming the peripheral clock is running at 133 MHz, the maximum period for the timer count is ((232-1) / 133 MHz) = 32.2 seconds. Default SCLK clock rate is 54 MHz. For more info see: PLL_CTL & PLL_DIV registers. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Timer Control – TIMER_ENABLE & TIMER_DISABLE
Digital Systems: Hardware Organization and Design 9/19/2018 Timer Control – TIMER_ENABLE & TIMER_DISABLE The Timer Enable (TIMER_ENABLE) register can be used to enable all three timers simultaneously. The register contains three “write-1-to-set” control bits, one for each timer. Correspondingly, the Timer Disable (TIMER_DISABLE) register contains three “write-1-to-clear” control bits to allow simultaneous or independent disabling of the three timers. Either the Timer Enable or the Timer Disable register can be read back to check the enable status of the timers. A 1 indicates that the corresponding timer is enabled. The timer starts counting three SCLK cycles after the TIMENx bit is set. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Timer Control: TIMER_STATUS
Digital Systems: Hardware Organization and Design 9/19/2018 Timer Control: TIMER_STATUS The Timer Status (TIMER_STATUS) register contains an Interrupt Latch bit (TIMILx) and an Overflow/Error Indicator bit (TOVF_ERRx) for each timer. These sticky bits are set by the timer hardware and may be polled by software. They need to be cleared by software explicitly, by writing a 1 to the bit. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Timer Configuration: TIMERx_CONFIG
Digital Systems: Hardware Organization and Design 9/19/2018 Timer Configuration: TIMERx_CONFIG To enable a timer’s interrupts, Set the IRQ_ENA bit in the timer’s Configuration (TIMERx_CONFIG) register and With the IRQ_ENA bit cleared, the timer does not set its Timer Interrupt latch (TIMILx) bits. Unmask the timer’s interrupt by setting the corresponding bits of the IMASK and SIC_IMASK registers. To poll the TIMILx bits without permitting a timer interrupt, programs can set the IRQ_ENA bit while leaving the timer’s interrupt masked. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Timer Configuration With interrupts enabled, To enable timer interrupts, set the IRQ_ENA bit in the proper Timer Configuration (TIMERx_CONFIG) register. Make sure that the interrupt service routine (ISR) clears the TIMILx latch before the RTI instruction, to ensure that the interrupt is not reissued. To make sure that no timer event is missed, the latch should be reset at the very beginning of the interrupt routine when in External Clock (EXT_CLK) mode. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Timer Registers Each timer provides four registers: TIMERx_CONFIG[15:0] – Timer Configuration register TIMERx_WIDTH[31:0] – Timer Pulse Width register TIMERx_PERIOD[31:0] – Timer Period register TIMERx_COUNTER[31:0] – Timer Counter register Three registers are shared between the three timers: TIMER_ENABLE[15:0] – Timer Enable register TIMER_DISABLE[15:0] – Timer Disable register TIMER_STATUS[15:0] – Timer Status register The size of accesses is enforced. A 32-bit access to a Timer Configuration register (16-bit register) or a 16-bit access to a Timer Pulse Width, Timer Period, or Timer Counter registers (32-bit registers) results in a Memory-Mapped Register (MMR) error. Both 16- and 32-bit accesses are allowed for the Timer Enable, Timer Disable, and Timer Status registers. On a 32-bit read, the upper word returns all 0s. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Initialization.c // // // Function: Init_Timers // // // // Parameters: None // // Return: None // // Description: This function initialises Timer0 for PWM mode // // It is used as reference for the 'shift-clock' // void Init_Timers(void) { *pTIMER0_CONFIG = 0x0019; *pTIMER0_PERIOD = 0x ; *pTIMER0_WIDTH = 0x ; *pTIMER_ENABLE = 0x0001; } TIMER0_CONFIG REGISTER INFO 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Timer Configuration Registers
Digital Systems: Hardware Organization and Design 9/19/2018 Timer Configuration Registers 0x0019 = PWM_OUT PERIOD_CNT IRQ_ENA GO BACK 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Initialization.c // // // Function: Init_Timers // // // // Parameters: None // // Return: None // // Description: This function initialises Timer0 for PWM mode // // It is used as reference for the 'shift-clock' // void Init_Timers(void) { *pTIMER0_CONFIG = 0x0019; *pTIMER0_PERIOD = 0x ; *pTIMER0_WIDTH = 0x ; *pTIMER_ENABLE = 0x0001; } TIMER0_PERIOD REGISTER INFO 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

TIMERx_PERIOD and TIMERx_WIDTH Registers
Digital Systems: Hardware Organization and Design 9/19/2018 TIMERx_PERIOD and TIMERx_WIDTH Registers Usage of the Timer Period register (TIMERx_PERIOD) and the Timer Pulse Width register (TIMERx_WIDTH) varies depending on the mode of the timer: In Pulse Width Modulation mode (PWM_OUT), both the Timer Period and Timer Pulse Width register values can be updated “on-the-fly” since the Timer Period and Timer Pulse Width (duty cycle) register values change simultaneously. In Pulse Width and Period Capture mode (WDTH_CAP), the Timer Period and Timer Pulse Width buffer values are captured at the appropriate time. The Timer Period and Timer Pulse Width registers are then updated simultaneously from their respective buffers. Both registers are read-only in this mode. In External Event Capture mode (EXT_CLK), the Timer Period register is writable and can be updated “on-the-fly.” The Timer Pulse Width register is not used. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Timer Period Registers
Digital Systems: Hardware Organization and Design 9/19/2018 Timer Period Registers 0x = = 223 = If fSCLK = 133 MHz ⇒ 223 / 133 MHz ≈ 0.06 sec Default fSCLK = 56 MHz ⇒ 223 / 56 MHz ≈ 0.15 sec 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Initialization.c // // // Function: Init_Timers // // // // Parameters: None // // Return: None // // Description: This function initialises Timer0 for PWM mode // // It is used as reference for the 'shift-clock' // void Init_Timers(void) { *pTIMER0_CONFIG = 0x0019; *pTIMER0_PERIOD = 0x ; *pTIMER0_WIDTH = 0x ; *pTIMER_ENABLE = 0x0001; } TIMER0_WIDTH REGISTER INFO 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Timer-Width Registers
Digital Systems: Hardware Organization and Design 9/19/2018 Timer-Width Registers Timer Width Register specifies the duty cycle of the cycle. When Timer Width register is set to Timer Period/2 value the duty cycle is 50%. 0x = = 222 = 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Initialization.c // // // Function: Init_Timers // // // // Parameters: None // // Return: None // // Description: This function initialises Timer0 for PWM mode // // It is used as reference for the 'shift-clock' // void Init_Timers(void) { *pTIMER0_CONFIG = 0x0019; *pTIMER0_PERIOD = 0x ; *pTIMER0_WIDTH = 0x ; *pTIMER_ENABLE = 0x0001; } TIMER_ENABLE 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Timer Enable Enabling Timer0 0x0001 = 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

External Bus Interface Unit (EBIU) Setup
Digital Systems: Hardware Organization and Design 9/19/2018 External Bus Interface Unit (EBIU) Setup FIO setup Timer setup EBIU setup Flash setup Interrupt configuration Endless loop waiting for Timer interrupt or Flag interrupt Architecture of a Respresentative 32 Bit Processor

External Bus Interface Unit
Digital Systems: Hardware Organization and Design 9/19/2018 External Bus Interface Unit The EBIU services requests for external memory from the Core or from a DMA channel. The priority of the requests is determined by the External Bus Controller. The address of the request determines whether the request is serviced by the EBIU SDRAM (synchronous dynamic random access memory) Controller or the EBIU Asynchronous Memory Controller. The EBIU is clocked by the system clock (SCLK). All synchronous memories interfaced to the processor operate at the SCLK frequency. The ratio between core frequency and SCLK frequency is programmable using a phase-locked loop (PLL) system memory-mapped registers (MMR). 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

EBIU Programming Model
Digital Systems: Hardware Organization and Design 9/19/2018 EBIU Programming Model This model is based on system memory-mapped registers used to program the EBIU. There are six control registers and one status register in the EBIU. They are: Asynchronous Memory Global Control register (EBIU_AMGCTL) Asynchronous Memory Bank Control 0 register (EBIU_AMBCTL0) Asynchronous Memory Bank Control 1 register (EBIU_AMBCTL1) SDRAM Memory Global Control register (EBIU_SDGCTL) SDRAM Memory Bank Control register (EBIU_SDBCTL) SDRAM Refresh Rate Control register (EBIU_SDRRC) SDRAM Control Status register (EBIU_SDSTAT) 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

The Asynchronous Memory Interface
Digital Systems: Hardware Organization and Design 9/19/2018 The Asynchronous Memory Interface The asynchronous memory interface allows a glueless interface to a variety of memory and peripheral types. These include SRAM, ROM, EPROM, flash memory, and FPGA/ASIC designs. Four asynchronous memory regions are supported. Each has a unique memory select associated with it, shown in Table 17-3. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Asynchronous Memory Bank Address Range
Digital Systems: Hardware Organization and Design 9/19/2018 Asynchronous Memory Bank Address Range 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 EBIU_AMGCTL Register The Asynchronous Memory Global Control register (EBIU_AMGCTL) configures global aspects of the controller. The EBIU_AMGCTL register should be the last control register written to when configuring the processor to access external memory-mapped asynchronous devices. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Initialization.c // // // Function: Init_EBIU // // // // Parameters: None // // Return: None // // Description: This function initializes and enables the asynchronous // // memory banks for the External Bus Interface Unit (EBIU), so // // that access to Flash A is possible // void Init_EBIU(void) { *pEBIU_AMBCTL0 = 0x7bb07bb0; *pEBIU_AMBCTL1 = 0x7bb07bb0; *pEBIU_AMGCTL = 0x000f; } Asynchronous Memory Global Control Register 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Asynchronous Memory Global Control Register EBIU_AMGCTL
Digital Systems: Hardware Organization and Design 9/19/2018 Asynchronous Memory Global Control Register EBIU_AMGCTL 0x000f = 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Initialization.c // // // Function: Init_EBIU // // // // Parameters: None // // Return: None // // Description: This function initializes and enables the asynchronous // // memory banks for the External Bus Interface Unit (EBIU), so // // that access to Flash A is possible // void Init_EBIU(void) { *pEBIU_AMBCTL0 = 0x7bb07bb0; *pEBIU_AMBCTL1 = 0x7bb07bb0; *pEBIU_AMGCTL = 0x000f; } Asynchronous Memory Control Register 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

EBIU_AMBCTL0 and EBIU_AMBCTL1 Registers
Digital Systems: Hardware Organization and Design 9/19/2018 EBIU_AMBCTL0 and EBIU_AMBCTL1 Registers The EBIU asynchronous memory controller has two Asynchronous Memory Bank Control registers: EBIU_AMBCTL0 and EBIU_AMBCTL1. They contain bits for counters for: setup, strobe, and hold time; bits to determine memory type and size; and bits to configure use of ARDY (Asynchronous Memory Ready Response) bit. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Asynchronous Memory Bank Control 0 Register
Digital Systems: Hardware Organization and Design 9/19/2018 Asynchronous Memory Bank Control 0 Register 0x7bb07bb0 = 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 External Memory Map The three SDRAM control registers must be initialized in order to use theMT48LC32M16 – 64 MB (32M x 16 bits) SDRAM memory of EZ-Kit Lite: EBIU_SDGCTL: SDRAM Memory Global Control register EBIU_SDBCTL: SDRAM Memory Bank Control register EBIU_SDRRC: SDRAM Refresh Rate Control register The External Memory Map supported by BF533 is provided in the Figure 17-1. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 EBIU_SDGCTL Register The SDRAM Memory Global Control register (EBIU_SDGCTL) includes all programmable parameters associated with the SDRAM access timing and configuration. Figure shows the EBIU_SDGCTL register bit definitions. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SDRAM Memory Global Control register: EBIU_SDGCTL
Digital Systems: Hardware Organization and Design 9/19/2018 SDRAM Memory Global Control register: EBIU_SDGCTL 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Initialization.c // // // Function: Init_EBIU // // // // Parameters: None // // Return: None // // Description: This function initializes and enables the asynchronous // // memory banks for the External Bus Interface Unit (EBIU), so // // that access to Flash A is possible // void Init_EBIU(void) { *pEBIU_AMBCTL0 = 0x7bb07bb0; *pEBIU_AMBCTL1 = 0x7bb07bb0; *pEBIU_AMGCTL = 0x000f; } 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

External Bus Interface Unit (EBIU) Setup
Digital Systems: Hardware Organization and Design 9/19/2018 External Bus Interface Unit (EBIU) Setup FIO setup Timer setup EBIU setup Flash setup Interrupt configuration Endless loop waiting for Timer interrupt or Flag interrupt Architecture of a Respresentative 32 Bit Processor

9/19/2018 Initialization.c // // // Function: Init_Flash // // // // Parameters: None // // Return: None // // Description: This function sets the pin direction of Port B in Flash A // // to output // // The LEDs on the ADSP-BF533 EZ-KIT are connected to Port B // void Init_Flash(void) { *pFlashA_PortB_Dir = 0x3f; } Direction Configuration 0x3f = The Direction register controls IO pins direction. This is a 8-bit read-write register. When a bit is 0, a corresponding pin functions as an input. When the bit is 1, a corresponding pin is an output. See Slide #13 for details or EZ-Kit Lite HRM. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Interrupt Configuration
Digital Systems: Hardware Organization and Design 9/19/2018 Interrupt Configuration FIO setup Timer setup EBIU setup Flash setup Interrupt configuration Endless loop waiting for Timer interrupt or Flag interrupt Architecture of a Respresentative 32 Bit Processor

9/19/2018 Program Sequencer Architecture of a Respresentative 32 Bit Processor

9/19/2018 Program Sequencer Controls all program flow Maintains loops Includes zero-overhead loop registers No cost for wrapping from loop bottom to loop top Maintains in-program branching Subroutines Jumps Interrupts and Exceptions 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Sequencer Related Registers
Digital Systems: Hardware Organization and Design 9/19/2018 Sequencer Related Registers 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Event Controller for Interrupts and Exceptions
Digital Systems: Hardware Organization and Design 9/19/2018 Event Controller for Interrupts and Exceptions Architecture of a Respresentative 32 Bit Processor

9/19/2018 Event Controller The Event Controller of the processor manages five types of activities or events: Emulation Reset Nonmaskable interrupts (NMI) Exceptions Interrupts (11) Note the word event describes all five types of activities. The Event Controller manages fifteen different events in all: Emulation, Reset, NMI, Exception, and eleven Interrupts. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Interrupts vs. Exceptions
Digital Systems: Hardware Organization and Design 9/19/2018 Interrupts vs. Exceptions An interrupt is an event that changes normal processor instruction flow and is asynchronous to program flow. In contrast, an exception is a software initiated event whose effects are synchronous to program flow. The event system is nested and prioritized. Consequently, several service routines may be active at any time, and a low priority event may be pre-empted by one of higher priority. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Event Controller The processor employs a two-level event control mechanism. The processor System Interrupt Controller (SIC) works with The Core Event Controller (CEC) to prioritize and control all system interrupts. The SIC provides mapping between the many peripheral interrupt sources and the prioritized general-purpose interrupt inputs of the core. This mapping is programmable, and individual interrupt sources can be masked in the SIC. The CEC supports nine (9) general-purpose interrupts (IVG7 – IVG15) in addition to the dedicated interrupt and exception events that are described in Table 4-6. It is recommended that the two lowest priority interrupts (IVG14 and IVG15) be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs (IVG7 – IVG13) to support the system. Refer to Table 4-6 for details. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Core Event Mapping 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 System Event Mapping 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Processor Event Controller
Digital Systems: Hardware Organization and Design 9/19/2018 Processor Event Controller Processor Event Controller Consists of 2 stages: The Core Event Controller (CEC) System Interrupt Controller (SIC) Conceptually: Interrupts from the peripherals arrive at SIC SIC routes interrupts directly to general-purpose interrupts of the CEC. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Core Event Controller (CEC)
Digital Systems: Hardware Organization and Design 9/19/2018 Core Event Controller (CEC) CEC supports 9 general-purpose interrupts: IVG15-7 IVG15-14 – (2) lowest priority interrupts for software handlers. IRVG13-7 – (7) highest to support peripherals. Additional dedicated interrupt and exception events. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

System Interrupt Controller (SIC)
Digital Systems: Hardware Organization and Design 9/19/2018 System Interrupt Controller (SIC) SIC provides mapping and routing of events: From: Peripheral interrupt sources To: Prioritized general-purpose interrupt inputs of the CEC. Note: Processor default mapping can be altered by the user via Interrupt Assignment Register (IAR). 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

BF533 System & Core Interrupt Controllers
Digital Systems: Hardware Organization and Design 9/19/2018 BF533 System & Core Interrupt Controllers System Interrupt Source IVG # 1 Event Source IVG # Core Event Name Highest PLL Wakeup interrupt IVG7 DMA error (generic) PPI error interrupt SPORT0 error interrupt SPORT1 error interrupt SPI error interrupt UART error interrupt RTC interrupt IVG8 DMA 0 interrupt (PPI) DMA 1 interrupt (SPORT0 RX) IVG9 DMA 2 interrupt (SPORT0 TX) DMA 3 interrupt (SPORT1 RX) DMA 4 interrupt (SPORT1 TX) DMA 5 interrupt (SPI) IVG10 DMA 6 interrupt (UART RX) DMA 7 interrupt (UART TX) Timer0 interrupt IVG11 Timer1 interrupt Timer2 interrupt PF interrupt A IVG12 PF interrupt B DMA 8/9 interrupt (MemDMA0) IVG13 DMA 10/11 interrupt (MemDMA1) Watchdog Timer Interrupt Emulator EMU Reset 1 RST Non Maskable Interrupt 2 NMI Exceptions 3 EVSW Reserved 4 - Hardware Error 5 IVHW Core Timer 6 IVTMR General Purpose 7 7 IVG7 General Purpose 8 8 IVG8 General Purpose 9 9 IVG9 General Purpose 10 10 IVG10 General Purpose 11 11 IVG11 General Purpose 12 12 IVG12 General Purpose 13 13 IVG13 General Purpose 14 14 IVG14 General Purpose 15 15 IVG15 P r i o r i t y Lowest 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

System Interrupt Processing
Digital Systems: Hardware Organization and Design 9/19/2018 System Interrupt Processing Referring to Figure 4-5, note when an interrupt (Interrupt A) is generated by an interrupt-enabled peripheral: SIC_ISR logs the request and keeps track of system interrupts that are asserted but not yet serviced (that is, an interrupt service routine hasn’t yet cleared the interrupt). SIC_IWR checks to see if it should wake up the core from an idled state based on this interrupt request. SIC_IMASK masks off or enables interrupts from peripherals at the system level. If Interrupt A is not masked, the request proceeds to Step 4. The SIC_IARx registers, which map the peripheral interrupts to a smaller set of general-purpose core interrupts (IVG7 – IVG15), determine the core priority of Interrupt A. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

System Interrupt Processing (cont.)
Digital Systems: Hardware Organization and Design 9/19/2018 System Interrupt Processing (cont.) ILAT adds Interrupt A to its log of interrupts latched by the core but not yet actively being serviced. IMASK masks off or enables events of different core priorities. If the IVGx event corresponding to Interrupt A is not masked, the process proceeds to Step 7. The Event Vector Table (EVT) is accessed to look up the appropriate vector for Interrupt A’s interrupt service routine (ISR). When the event vector for Interrupt A has entered the core pipeline, the appropriate IPEND bit is set, which clears the respective ILAT bit. Thus, IPEND tracks all pending interrupts, as well as those being presently serviced. When the interrupt service routine (ISR) for Interrupt A has been executed, the RTI instruction clears the appropriate IPEND bit. However, the relevant SIC_ISR bit is not cleared unless the interrupt service routine clears the mechanism that generated Interrupt A, or if the process of servicing the interrupt clears this bit. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Interrupt Processing Block Diagram
Digital Systems: Hardware Organization and Design 9/19/2018 Interrupt Processing Block Diagram It should be noted that emulation, reset, NMI, and exception events, as well as hardware error (IVHW) and core timer (IVTMR) interrupt requests, enter the interrupt processing chain at the ILAT level and are not affected by the system-level interrupt registers (SIC_IWR, SIC_ISR, SIC_IMASK, SIC_IARx). When the interrupt service routine (ISR) for Interrupt A has been executed, the RTI instruction clears the appropriate IPEND bit. However, the relevant SIC_ISR bit is not cleared unless the interrupt service routine clears the mechanism that generated Interrupt A, or if the process of servicing the interrupt clears this bit. IMASK masks off or enables events of different core priorities. If the IVGx event corresponding to Interrupt A is not masked, the process proceeds to Step 7. The Event Vector Table (EVT) is accessed to look up the appropriate vector for Interrupt A’s interrupt service routine (ISR). When the event vector for Interrupt A has entered the core pipeline, the appropriate IPEND bit is set, which clears the respective ILAT bit. Thus, IPEND tracks all pending interrupts, as well as those being presently serviced. ILAT adds Interrupt A to its log of interrupts latched by the core but not yet actively being serviced. SIC_ISR logs the request and keeps track of system interrupts that are asserted but not yet serviced (that is, an interrupt service routine hasn’t yet cleared the interrupt). SIC_IWR checks to see if it should wake up the core from an idled state based on this interrupt request. SIC_IMASK masks off or enables interrupts from peripherals at the system level. If Interrupt A is not masked, the request proceeds to Step 4. The SIC_IARx registers, which map the peripheral interrupts to a smaller set of general-purpose core interrupts (IVG7 – IVG15), determine the core priority of Interrupt A. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Interrupt Service Routine
Digital Systems: Hardware Organization and Design 9/19/2018 Interrupt Service Routine ISR address is stored in the Event Vector Table Used as the next fetch address when the event occurs Program Counter (PC) address is saved to a register RETI, RETX, RETN, RETE, based on event ISR always concludes with “Return” Instruction RTI, RTX, RTN, RTE (respectively) When executed, PC is loaded with address stored in RETI, RETX, RETN, or RETE to continue app code Optional nesting of higher-priority interrupts possible See app. note EE-192, which covers writing interrupt routines in C ( 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

System Peripheral Interrupts
Digital Systems: Hardware Organization and Design 9/19/2018 System Peripheral Interrupts The processor system has numerous peripherals, which therefore require many supporting interrupts. Table 4-7 lists: The Peripheral Interrupt source The Peripheral Interrupt ID used in the System Interrupt Assignment registers (SIC_IARx). See “System Interrupt Assignment Registers (SIC_IARx)” on page 4-30 of BF533 HRM. The general-purpose interrupt of the core to which the interrupt maps at reset The Core Interrupt ID used in the System Interrupt Assignment registers (SIC_IARx). See “System Interrupt Assignment Registers (SIC_IARx)” on page 4-30 of BF533 HRM. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Peripheral Interrupt Source at Reset State
Digital Systems: Hardware Organization and Design 9/19/2018 Peripheral Interrupt Source at Reset State 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Initialization of Interrupts
Digital Systems: Hardware Organization and Design 9/19/2018 Initialization of Interrupts If the default assignments shown in Table 4-7 are acceptable, then interrupt initialization involves only: Initialization of the core Event Vector Table (EVT) vector address entries. Why is this needed? Initialization of the IMASK register Unmasking the specific peripheral interrupts in SIC_IMASK that the system requires 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Initialization of Core Vector Table
Digital Systems: Hardware Organization and Design 9/19/2018 Initialization of Core Vector Table The Event Vector Table (EVT) is a hardware table with sixteen entries that are each 32 bits wide. The EVT contains an entry for each possible core event. Entries are accessed as MMRs, and Each entry can be programmed at reset with the corresponding vector address for the interrupt service routine. When an event occurs, instruction fetch starts at the address location in the EVT entry for that event. The processor architecture allows unique addresses to be programmed into each of the interrupt vectors; that is, interrupt vectors are not determined by a fixed offset from an interrupt vector table base address. This approach minimizes latency by not requiring a long jump from the vector table to the actual ISR code. Table 4-9 lists events by priority. Each event has a corresponding bit in the event state registers: ILAT, IMASK, and IPEND. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Core Event Vector Table
Digital Systems: Hardware Organization and Design 9/19/2018 Core Event Vector Table 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Initialization.c // // // Function: Init_Interrupts // // // // Parameters: None // // Return: None // // Description: This function initializes the interrupts for Timer0 and // // FlagA (PF8) // void Init_Interrupts(void) { // assign core IDs to interrupts *pSIC_IAR0 = 0xffffffff; *pSIC_IAR1 = 0xffffffff; *pSIC_IAR2 = 0xffff5ff4; // Timer0 -> ID4; FlagA -> ID5 // assign ISRs to interrupt vectors register_handler(ik_ivg11, Timer0_ISR); // Timer0 ISR -> IVG 11 register_handler(ik_ivg12, FlagA_ISR); // FlagA ISR -> IVG 12 // enable Timer0 and FlagA interrupt *pSIC_IMASK = 0x ; } System Interrupt Assignment Register 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

System Interrupt Assignment Registers (SIC_IARx)
Digital Systems: Hardware Organization and Design 9/19/2018 System Interrupt Assignment Registers (SIC_IARx) The relative priority of peripheral interrupts can be set by mapping the peripheral interrupt to the appropriate general-purpose interrupt level in the core. The mapping is controlled by the System Interrupt Assignment register settings, as detailed in Figure 4-9, Figure 4-10, and Figure 4-11. If more than one interrupt source is mapped to the same interrupt, they are logically OR-ed, with no hardware prioritization. Software can prioritize the interrupt processing as required for a particular system application. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Mapping of Values in SIC_IARx Register to General Purpose Interrupt
Digital Systems: Hardware Organization and Design 9/19/2018 Mapping of Values in SIC_IARx Register to General Purpose Interrupt Table 4-8 defines the value to write in SIC_IARx to configure a peripheral for a particular IVG priority. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

System Interrupt Assignment Register
Digital Systems: Hardware Organization and Design 9/19/2018 System Interrupt Assignment Register 0xffffffff = 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

System Interrupt Assignment Register
Digital Systems: Hardware Organization and Design 9/19/2018 System Interrupt Assignment Register 0xffff5ff4 = PF A Interrupt Timer 0 Interrupt 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Initialization.c // // // Function: Init_Interrupts // // // // Parameters: None // // Return: None // // Description: This function initializes the interrupts for Timer0 and // // FlagA (PF8) // void Init_Interrupts(void) { // assign core IDs to interrupts *pSIC_IAR0 = 0xffffffff; *pSIC_IAR1 = 0xffffffff; *pSIC_IAR2 = 0xffff5ff4; // Timer0 -> ID4; FlagA -> ID5 // assign ISRs to interrupt vectors register_handler(ik_ivg11, Timer0_ISR); // Timer0 ISR -> IVG 11 register_handler(ik_ivg12, FlagA_ISR); // FlagA ISR -> IVG 12 // enable Timer0 and FlagA interrupt *pSIC_IMASK = 0x ; } See Table for Peripheral Interrupt Source at Reset 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Interrupt Handler Support
Digital Systems: Hardware Organization and Design 9/19/2018 Interrupt Handler Support The Blackfin C/C++ compiler provides support for interrupts and other events used by the Blackfin processor architecture (see Table 1-25 of VisualDSP C/C++ Compiler and Library Manual for Blackfin Processors). The Blackfin system has several different classes of events, not all of which are supported by the ccblkfn compiler. Handlers for these events are called Interrupt Service Routines (ISRs). The compiler provides facilities for defining an ISR function, registering it as an event handler, and for obtaining the saved processor context. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Defining an ISR To define a function as an ISR, the sys/exception.h header must be included and the function must be declared and defined using macros defined within this header file. Where is this file included in the LED Lab #1 example? There is a macro for each of the three kinds of events the compiler supports: EX_INTERRUPT_HANDLER EX_EXCEPTION_HANDLER EX_NMI_HANDLER Which macro was used in Lab #1 exercise? By default, the ISRs generated by the compiler are not re-entrant; they disable the interrupt system on entry, and re-enable it on exit. You may also define ISRs for interrupts which are re-entrant, and which re-enable the interrupt system soon after entering the ISR. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Example #include <sys/exception.h> static int number_of_interrupts; EX_INTERRUPT_HANDLER(my_isr) { number_of_interrupts++; } This example declares and defines my_isr() as a handler for interrupt-type events. The macro used for defining the ISR is also suitable for declaring it as a prototype: EX_INTERRUPT_HANDLER(my_isr); 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Registering an ISR ISRs, once defined, can be registered in the Event Vector Table (EVT) using the register_handler_ex() function or the register_handler() function, both of which also update the IMASK register so that interrupt can take effect. Only the register_handler_ex() function will be discussed here, as it is an extended version of the register_handler() function. Refer to “register_handler_ex” on page of VisualDSP C/C++ Compiler and Library Manual for Blackfin Processors for more information about it. The register_handler_ex() function takes three parameters, defining the event, the ISR, and whether the interrupt should be enabled, disabled, or left in its current state. It also returns the previously registered ISR (if any). The event is specified using the interrupt_kind enumeration from exception.h. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Registering an ISR typedef enum { ik_emulation, ik_reset, ik_nmi, ik_exception, ik_global_int_enable, ik_hardware_err, ik_timer, ik_ivg7, ik_ivg8, ik_ivg9, ik_ivg10, ik_ivg11, ik_ivg12, ik_ivg13, ik_ivg14, ik_ivg15 } interrupt_kind; ex_handler_fn register_handler_ex( interrupt_kind kind, ex_handler_fn fn, int enable); Which enumeration types were used in the LAB # exercise? 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 register_handler Register event handlers Synopsis #include <sys/exception.h> ex_handler_fn register_handler (interrupt_kind kind, ex_handler_fn fn); Description The register_handler function determines how the hardware event kind is handled. This is done by registering the function pointed to by fn as a handler for the event and updating the IMASK register so that interrupt can take effect. The kind event is an enumeration identifying each of the hardware events—interrupts and exceptions—accepted by the Blackfin processor. Note: The register_handler_ex function provides an extended and more functional interface than register_handler. For the values for kind, refer to “Registering an ISR” on page of VisualDSP C/C++ Compiler and Library Manual for Blackfin Processors presented also in the previous slide. The fn must be one of the values are listed in the table in the next slide. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Table of fn values Which function value was used in the Lab #1 exercise? 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Initialization.c // // // Function: Init_Interrupts // // // // Parameters: None // // Return: None // // Description: This function initializes the interrupts for Timer0 and // // FlagA (PF8) // void Init_Interrupts(void) { // assign core IDs to interrupts *pSIC_IAR0 = 0xffffffff; *pSIC_IAR1 = 0xffffffff; *pSIC_IAR2 = 0xffff5ff4; // Timer0 -> ID4; FlagA -> ID5 // assign ISRs to interrupt vectors register_handler(ik_ivg11, Timer0_ISR); // Timer0 ISR -> IVG 11 register_handler(ik_ivg12, FlagA_ISR); // FlagA ISR -> IVG 12 // enable Timer0 and FlagA interrupt *pSIC_IMASK = 0x ; } Unmasking of the Interrupt by setting corresponding bits in SIC_IMASK register. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 SIC_IMASK Register The System Interrupt Mask register (SIC_IMASK, shown in Figure 4-8 Blacfin BF533 HRM) allows masking of any peripheral interrupt source at the System Interrupt Controller (SIC), independently of whether it is enabled at the peripheral itself. A reset forces the contents of SIC_IMASK to all 0s to mask off all peripheral interrupts. Writing a 1 to a bit location turns off the mask and enables the interrupt. Although this register can be read from or written to at any time (in Supervisor mode), it should be configured in the reset initialization sequence before enabling interrupts. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 SIC_IMASK Register 0x = PF Interrupt A Timer 0 Interrupt 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Servicing Interrupts Architecture of a Respresentative 32 Bit Processor

9/19/2018 ISR.c: ISR for Timer0 #include "BF533 Flags.h" // // // Function: Timer0_I // // // // Parameters: None // // Return: None // // Description: This ISR is executed every time Timer0 expires // // The old LED pattern is shifted by one; the direction // // depends on the state of sLight_Move_Direction, which is // // changed in FlagA_ISR // EX_INTERRUPT_HANDLER(Timer0_ISR) { static unsigned char ucActive_LED = 0x01; // confirm interrupt handling *pTIMER_STATUS = 0x0001; // shift old LED pattern by one if(sLight_Move_Direction) if((ucActive_LED = ucActive_LED >> 1) == 0x00) ucActive_LED = 0x20; } else if((ucActive_LED = ucActive_LED << 1) == 0x40) ucActive_LED = 0x01; // write new LED pattern to Port B *pFlashA_PortB_Data = ucActive_LED; 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Timer Status Register In the discussion about the BF533 Timers it was mentioned that the following three registers are shared between the three timers: TIMER_ENABLE[15:0] – Timer Enable register TIMER_DISABLE[15:0] – Timer Disable register TIMER_STATUS[15:0] – Timer Status register 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Timer Status Register The Timer Status register (TIMER_STATUS) indicates the status of all three timers and is used to check the status of all three timers with a single read. Status bits are sticky and write-1-to-clear (W1C). The TRUNx bits can clear themselves, which they do when a PWM_OUT mode timer stops at the end of a period. During a Status Register read access, all reserved or unused bits return a 0. Each Timer generates a unique interrupt request signal, which is gated by the corresponding IRQ_ENA bit in the TIMERx_CONFIG register. The shared Timer Status register (TIMER_STATUS) latches these interrupts so the user can determine the interrupt source without reference to the unique interrupt signal (for example, in the case where all three timers have been assigned to the same interrupt priority). Interrupt bits are sticky and must be cleared by the interrupt service routine (ISR) to assure that the interrupt is not reissued. The TIMILx bits work along with the IRQ_ENA bit of the Timer Configuration register to indicate interrupt requests. If an interrupt condition or error occurs and IRQ_ENA is set, then the TIMILx bit is set and the interrupt to the core is asserted. This interrupt may be masked by the system interrupt controller. If an interrupt condition or error occurs and IRQ_ENA is cleared, then the TIMILx bit is not set and the interrupt is not asserted. If TIMILx is already set and IRQ_ENA is written to 0, TIMILx stays set and the interrupt stays asserted. (See Figure on page of the manual). (ADSP-BF533 Blackfin Processor Hardware Reference: Timers) 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Timer Status Register The read value of the TRUNx bits reflects the timer slave enable status in all modes: TRUNx set indicates running and TRUNx cleared indicates stopped. While reading the TIMENx or TIMDISx bits in the TIMER_ENABLE and TIMER_DISABLE registers will reflect whether a timer is enabled, the TRUNx bits indicate whether the timer is actually running. In WDTH_CAP and EXT_CLK modes, reads from TIMENx and TRUNx always return the same value. A write-1-to clear W1C operation to the TIMER_DISABLE register disables the corresponding timer in all modes. In PWM_OUT mode, a disabled timer continues running until the ongoing period (PERIOD_CNT = 1) or pulse (PERIOD_CNT = 0) completes. During this final period the TIMENx bit returns 0, but the TRUNx bit still reads as a 1. (See Figure on page of the manual). In this state only, TRUNx becomes a write-1-to clear W1C bit. During this final period with the timer disabled, writing a 1 to TRUNx clears TRUNx and stops the timer immediately without waiting for the timer counter to reach the end of its current cycle. Writing the TRUNx bits has no effect in other modes or when a timer has not been enabled. Writing the TRUNx bits to 1 in PWM_OUT mode has no effect on a timer that has not first been disabled. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Timer Status Register (TIMER_STATUS)
Digital Systems: Hardware Organization and Design 9/19/2018 Timer Status Register (TIMER_STATUS) 0x0001 = 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 ISR.c: ISR for Timer0 #include "BF533 Flags.h" // // // Function: Timer0_I // // // // Parameters: None // // Return: None // // Description: This ISR is executed every time Timer0 expires // // The old LED pattern is shifted by one; the direction // // depends on the state of sLight_Move_Direction, which is // // changed in FlagA_ISR // EX_INTERRUPT_HANDLER(Timer0_ISR) { static unsigned char ucActive_LED = 0x01; // confirm interrupt handling *pTIMER_STATUS = 0x0001; // shift old LED pattern by one if(sLight_Move_Direction) if((ucActive_LED = ucActive_LED >> 1) == 0x00) ucActive_LED = 0x20; } else if((ucActive_LED = ucActive_LED << 1) == 0x40) ucActive_LED = 0x01; // write new LED pattern to Port B *pFlashA_PortB_Data = ucActive_LED; 0x0001 = 0x01 >> 1 = >> 1 0x = x = 0x01 << 1 = << 1 0x = Send LED Pattern to FlashA PortB. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

ISR.c: ISR for Push-Buttons
Digital Systems: Hardware Organization and Design 9/19/2018 ISR.c: ISR for Push-Buttons // // // Function: FlagA_ISR // // // // Parameters: None // // Return: None // // Description: This ISR is called every time the button connected to PF8 // // is pressed. // // The state of flag sLight_Move_Direction is changed, so the // // shift-direction for the LED pattern in Timer0_ISR changes. // EX_INTERRUPT_HANDLER(FlagA_ISR) { // confirm interrupt handling *pFIO_FLAG_C = 0x0100; // toggle direction of moving light sLight_Move_Direction = ~sLight_Move_Direction; } 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

FIO_FLAG_S, FIO_FLAG_C, and FIO_FLAG_T Registers
Digital Systems: Hardware Organization and Design 9/19/2018 FIO_FLAG_S, FIO_FLAG_C, and FIO_FLAG_T Registers As discussed in FIO Set-up section, the Flag Set register (FIO_FLAG_S), Flag Clear register (FIO_FLAG_C), and Flag Toggle register (FIO_FLAG_T) are used to: Set, clear or toggle the output state associated with each output PFx pin Clear the latched interrupt state captured from each input PFx pin 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 FIO_FLAG_C Register 0x0100 = 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

ISR.c: ISR for Push-Buttons
Digital Systems: Hardware Organization and Design 9/19/2018 ISR.c: ISR for Push-Buttons // // // Function: FlagA_ISR // // // // Parameters: None // // Return: None // // Description: This ISR is called every time the button connected to PF8 // // is pressed. // // The state of flag sLight_Move_Direction is changed, so the // // shift-direction for the LED pattern in Timer0_ISR changes. // EX_INTERRUPT_HANDLER(FlagA_ISR) { // confirm interrupt handling *pFIO_FLAG_C = 0x0100; // toggle direction of moving light sLight_Move_Direction = ~sLight_Move_Direction; } 0x0100 = Toggle direction flag. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Blackfin Home Page: Blackfin Development Tools Technical Library Blackfin Code Examples Blackfin Processor Family Manuals Evaluation Kits & Reference Boards Blackfin Online Learning & Development (BOLD) uClinux Blackfin User's Community 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Blackfin DSP Manuals Processor Manuals Software Manuals Evaluation Kit Manuals Emulator Manuals 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

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Microcomputer Systems 1

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