1. 8253 Timer
In software programming of 8085, it has been shown that a delay subroutine can be programmed to introduce a predefined time delay.
The delay is achieved by decrementing a count value in a register using instructions.
The disadvantage of this software approach is that the processor is locked in the delay loop and the precious processor time is wasted in just counting.
This advantage can be overcome by using the hardware timer and interrupts.
This can’t be easily interfaced with the microprocessor. So, Intel has produced programmable timer devices namely IC 8253 and IC 8254.
These devices can be programmed to generate different types of delay signals and also count external signals.

2. Features of IC 8253
Timer ICs 8253 and 8254 are manufactured by Intel with the similar operating functions can be operated at frequency of up to 8MHz whereas 8253 can be operated only up to a maximum frequency of 2.6MHz.
Other counter/timer functions that are also common to be implemented with the 8253 are Programmable frequency square wave Generator, Event Counter, Real Time Clock, Digital One-Shot and Complex Motor Controller.
Generation of accurate time delay
Three independent 16-bit down counters called as channels
Six different programmable operating modes
Timer or counter operation.
Can count in binary or BCD
Can be used to interrupt the processor.
Single +5V supply
Can operate from DC to 2.6MHz.

3. Block Diagram of IC 8253

4. Pin Details of IC 8253

5. the three independent 16-bit timers named as Counter 0, Counter 1 and Counter 2.
These counters have the programmable feature meaning that the count value can be loaded initially using the data from the data bus. It can be made to start counting and stop counting using software instructions written to the control register.
The count value can also be read using the data bus to the microprocessor.

6. Each counter has 2 input pins - CLK (clock input) and GATE - and 1-pin, OUT, for data output. The control input line GATE is used to start or stop the counting operation.
The OUT signal from each counter can be used to indicate the completion of required counting or timing operation and also to interrupt the processor.
An 8-bit data bus is available on the 8253 pins to interface the IC with the microprocessor.

7. A control signal is used to select the chip
A control signal is used to select the chip. This active low signal can be activated using the address lines and the decoder. In addition, the 8253 requires two address lines A0 and A1 to be issued from the 8085 hardware.
This address lines are used to select one of four registers in the 8253 – Three counters and one control register. and control signals are issued by the processor to indicate whether it is reading or writing to 8253 registers.

9. Operating modes and control word of IC 8253
The complete operation of the 8253 is programmed by the systems software or the programmer. The programmer configures the 8253 to match his requirements.
A set of control words must be sent out by the programmer to initialize each counter of the These control words program the MODE, Loading sequence and selection of binary or BCD counting.
Then the programmer initializes one of the counters of the 8253 with the desired quantity.

10. Then upon proper command or control word, the 8253 will count-out the delay and interrupt the CPU when it has completed its tasks. It is easy to see that the software overhead is minimal and that multiple delays can easily be maintained by assignment of interrupt priority levels.
The normal procedure for software control of 8253 has three main steps listed below.

11. Write the proper control word to the control register of 8253 for each counter used.
Write the initial count value into the counter register.
Apply clock pulses to the counter.
Check the count value for proper operation or check the Out signal of 8253 counter or Program for interrupt from the counter.

12. Each counter of the 8253 is individually programmed by writing a control word into the Control Word Register.
The control word format is shown in Table The LSB D0 bit is used to select whether the counter should count is binary or BCD format.
The next three bits M0 to M2 decides one of 6 operating modes for the counter selected. RL0 and RL1 bits decide read or load operation to be performed on the counter.

13. The counter can be made to count continuously, but program can write a control word to latch the count value for checking in the software.
Similarly, initial setup can define whether a 8 bit value is loaded into the counter or 16 bit value is loaded into the counter.
MSB 2 bits SC0 and SC1 will decide the counter for mode and operation setting.

16. Mode 0: Interrupt on Terminal Count
In mode 0, the counter will start counting from the initial COUNT value loaded into it, down to 0
Counting rate is according to the input clock frequency.
The signal on OUT pin is made low by 8253 after the Control Word is written, and counting starts one clock cycle after the COUNT value is loaded to the counter.

17. The voltage on the OUT pin remains low until the counter reaches 0
The voltage on the OUT pin remains low until the counter reaches 0. When the count value reaches zero, OUT will be set high and remain high until the counter is reloaded or the Control Word is written.
This mode 0 operation is one time operation and the OUT signal indicates the terminal condition of the required count operation.
The GATE input signal of the corresponding counter either enables or disables the counting operation.

18. Waveform of counter operation in mode 0

19. Timer interface using Interrupt method
Here the counter is initialized and then the counter starts counting. In mode 2, the counter gives a logic 0 pulse for a clock period after the count is over.
This clock pulse is used as an interrupt signal to 8085 processor. It is assumed that a timer IC 8253 is interfaced to the processor 8085 at the addresses 30H – 33H and IC 8255 is interfaced at the addresses 40H - 43H with two seven segment displays interfaced to the Port A

20. This interface uses interrupt feature of 8085 to increment the count value in the displays at Port A of 8255.
The timer IC is programmed to give an interrupt signal at every second. To achieve this, the 8253 is programmed in mode 2 and generate an OUT signal after every second. Then in the interrupt service routine, the display is incremented.

21. Here in this example, the OUT signal from 8253 is connected to the RST 5.5 interrupt line of 8085 as shown in figure The RST5.5 requires an active high signal. But 8253 gives out an active low signal whenever the counting is over in mode2.
So, an inverter is connected in between. The clock frequency applied at CLK0 is selected as 1 kHz signal. And GATE0 is connected to logic 1. The program for the same is given below.

22. Interfacing 8253 Timer 0 in Interrupt driven mode
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24. 8259 Programmable Interrupt Controller
In a system to read ASCII characters from a Keyboard on interrupt basis or to detect emergency or job done intimations, Interrupt handling routines are used.
For this, a processor will have maskable or non-maskable interrupts. But the processor has limited number of hardware interrupts.
For applications that use interrupts from multiple sources, the hardware can use external device called “Programmable Interrupt Controller” or “Priority Interrupt Controller”.

25. The Intel 8259 is a Programmable Interrupt Controller (PIC) designed and developed for use with the Intel 8085 and Intel 8086 microprocessors.
The family originally consisted of the 8259, 8259A, and 8259B PICs, though a number of manufacturers make a wide range of compatible chips.

26. Features and Architecture of 8259
The basic operation of Interrupt mechanism lies in calling a subroutine whenever a hardware interrupt signal is activated.
When more number of interrupt sources are present, the process of calling interrupt subroutine involves priority resolving and checking mask for interrupts.
The main purpose of using 8259 interrupt controller is also to do the same task of calling interrupt service routine based on the interrupt priority and masks.
The 8259 acts as a multiplexer, combining multiple interrupt input sources into a single interrupt request to the processor.

27. The main features of 8259 are listed below.
8 levels of interrupts.
Can be cascaded in master-slave configuration to handle up to 64 interrupts.
Internal priority resolver- Fixed priority mode and rotating priority mode.
Individually maskable interrupts.
Polled and vectored mode.
Starting address of ISR or vector number is programmable.
No clock required.

28. The interrupts in the controller are individually maskable
The interrupts in the controller are individually maskable. The modes and masks can be changed dynamically.
It accepts interrupt request from external devices, determines priority, and checks whether incoming priority is greater than current level being serviced and issue interrupt signal and the corresponding vector address to the processor.

29. In 8085 system, it provides 3 byte CALL instruction
In 8085 system, it provides 3 byte CALL instruction. In 8086 based systems, it provides 8 bit vector number.
It can be operated in polled and vectored mode. The starting address of ISR or vector number is programmable. No clock is required for the IC.

30. Using the Read / Write logic, 8259 is interfaced with the processor
Using the Read / Write logic, 8259 is interfaced with the processor. The data bus lines D0-D7 are connected to the data lines of the processor chip will be selected using the line.
Address line A0 is used to select the control word or the data word. If A0 =Low, then the controller selects writing a command word / reading a status. If A0 =1, then the controller selects another register for writing the initialization words.

31. The Control logic has INT and
The Control logic has INT and . The INT output pin is used to interrupt the CPU. The 8259 receives the interrupt acknowledge pulse from the CPU through its input can receive interrupt signals from eight different sources on the lines IR0-IR7.
When these lines go high, the requests are stored in the Interrupt Request Register. The Interrupt Service Register (ISR) stores all the levels that are currently being serviced.

32. The Interrupt Mask Register (IMR) stores the masking bits of the interrupt lines to be masked. The Priority Resolver examines the interrupt registers and determines whether the INT should be sent to the microprocessor or not.
The Cascade buffer or Comparator is used to expand the number of interrupt levels by cascading two or more 8259s.

33. 8259 Internal Block Diagram

34. 8259 can be used in cascaded mode
8259 can be used in cascaded mode. Up to eight slave 8259s may be cascaded to a master 8259 to provide up to 64 IRQs. 8259s are cascaded by connecting the INT line of one slave 8259 to the IRQ line of one master 8259.
There are three registers,
An Interrupt Mask Register (IMR)
An Interrupt Request Register (IRR) and
An In-Service Register (ISR).

35. End Of Interrupt (EOI) operations support specific EOI, non-specific EOI, and auto-EOI. A specific EOI specifies the IRQ level it is acknowledging in the ISR. A non-specific EOI resets the IRQ level in the ISR. Auto-EOI resets the IRQ level in the ISR immediately after the interrupt is acknowledged.
Edge and level interrupt trigger modes are supported. Fixed priority and rotating priority modes are supported. The 8259 may be configured to work with an 8085 or an 8086.

36. Pin Diagram and Details of 8259

37. The main signals on an 8259 are as follows:
Eight interrupt input request lines named IRQ0 - IRQ7
An interrupt request output line named INTR
Interrupt acknowledgment line named INTA
D0 - D7 for communicating the interrupt level or vector offset.
Other connectors include CAS0 through CAS2 for cascading between 8259s.

38. D0-D7 - Bi-directional, tristate, buffered data lines
D0-D7 - Bi-directional, tristate, buffered data lines. Connected to data bus directly or through buffers
- Active low read control signal
- Active low write control signal
A0 - Address input line, used to select control register
- Active low chip select line
CAS 0-2-Bi-directional, 3 bit cascade lines. In master mode, PIC places slave ID no. on these lines. In slave mode, the PIC reads slave ID no. from master on these lines. It may be regarded as slave-select.

39. - Slave program / enable
- Slave program / enable. In non-buffered mode, it is SP- input, used to distinguish master/slave PIC. In buffered mode, it is output line used to enable buffers
INT - Interrupt line, connected to INTR of microprocessor
- Interrupt acknowledgement, active low signal received from microprocessor
IR0-7 - Asynchronous IRQ input lines, generated by peripherals.

40. Initialization of 8259
To service the interrupt requests the interrupt controller should be initialized by writing control words in the control register.
It requires two types of control words: Initialization Command Words (ICWs) and Operational Command Words (OCWs). The ICWs are used to set up proper conditions and specify Restart vector location. The OCWs are used for masking interrupts setting up status read operations etc.
The 8259 can be initialized with four ICWs of which the first two are essential and other two are optional based on the modes being used.
These words must be issued in a given sequence.

41. Once initialized the interrupt controller can be set up to operate in various modes using three different operational command words
Operation command words can be written into 8259 at any time to perform the specific functions.

42. Ready to Accept Interrupts
ICW1
ICW2
In Cascade Mode
ICW3
Is ICW4 Needed
ICW4
Ready to Accept Interrupts No
Yes

43. ICW-1 must be written first in to 8259 with A0=0
ICW-1 must be written first in to 8259 with A0=0. This should be followed by ICW-2.
The bit definitions are self explanatory. D2 bit - ADI is used to set Address interval in the interrupt vector table.
It is used only in 8085, not in If it is 1, then ISR addresses are 4 bytes apart (0200, 0204, etc) or if it is 0, then ISR addresses are 8 byte apart (0200, 0208, etc).

44. The D3 –LTIM is used to indicate the details about the hardware signal used in IRQ lines. It is used to select whether the signal is level triggered or edge triggered.
D4-D7 bits are used set the A5-A7 of the ISR vector address lower byte segment. The lower byte is A7-A0 of which A7, A6, A5 are provided by D7-D5 of ICW1 (if ADI=1), or A7, A6 are provided if ADI=0. A4-A0 (or A5-A0) are set by 8259 itself: It is applicable for 8085 only.

46. Format of ICW - 2 (Initialization Command Word - 2)
ICW 2 is used to set the higher order 8 bits of the Interrupt vector addresses in the case of For 8086, it defines the 8-bit vector address. This initialization word is written into 8259 with A0=1.
Format of ICW - 3 (Initialization Command Word - 3)
ICW-3 is required only when the PIC 8259 is connected in cascaded mode i.e. more than one 8259 is connected in a system. This initialization word is written into 8259 with A0=1.There two different formats of ICW-3 – one for the master and the other for the slave.

48. For the Master mode, the ICW-3 is used to indicate whether a slave 8259 is connected in the interrupt request line IRQ or not. If a bit is 1, it indicates that slave is present on that interrupt request line. A 0 in a bit position indicates it is direct interrupt request from an external device.
For the Slave modem ICW-3 assigns the slave with a specific ID number. So the LSB 3 bits are used for that. ID2-ID0 is the slave ID number. For example, slave 4 has ICW3=04h ( ).

49. Format of ICW - 4 (Initialization Command Word
ICW-4 is necessary only when it is clearly specified in the ICW-1. It is used to indicate whether 8085 is used or 8086 is used in the system. It specifies the end of interrupt mode and buffered or non buffered and the use of special fully nested mode. The details are given in the figure This initialization word is written into 8259 with A0=1.

51. Format of OCW- 1 (Operational Command Word - 1)
OCW-1 is written in to 8259 with A0=1. This word specifies the masking of Interrupt Requests IR0-IR7. The eight bits of the OCW-1 are used to mask the eight interrupts with LSB D0 masking IR0 and MSB masking IR7. A particular interrupt IRn is masked by setting Mn to 1; mask cleared by setting corresponding Mn to 0 (n=0 - 7).

53. OCW2 (Operational Command Word Two)
OCW-2 is written with the A0= 1 in to This word is used to specify priorities of interrupts and issue of end of Interrupt commands. OCW-2 is usually written to reset the bit in the in-service register. Normally, a bit is set in the in-service register whenever the corresponding interrupt is serviced. This is generally written at the end of the interrupt service routine.

54. The OCW-2 can be programmed for Non specific end of Interrupt mode with the data ( ) to automatically reset the in service register (ISR) bit.
The programmer can also use OCW-2 to reset a specific ISR bit. The OCW-2 can also be used to rotate the priorities of the interrupts. Figure 7.61 shows the bit format of OCW-2.

57. Operation of 8259
The following steps show how interrupt handling is done when an external device places interrupt request on the IR lines of It is assumed that the system has a single 8259 chip.
One or more of the IR lines may go high.
Corresponding IRR bit is set.
8259 evaluates the request based masking and priority
8259 sends interrupt request - INT to the CPU.

58. CPU sends
Highest priority ISR is set and IRR is reset in 8259.
8259 releases CALL instruction on data bus.
CALL causes CPU to initiate two more s. The Processor will send two interrupt acknowledge pulses on its pin to the pin of The pulses tell 8259 to send desired interrupt type to the processor onto the data bus releases the subroutine address, first lower byte and then higher byte.
The Interrupt service routine is executed in the processor with the following steps.

59. --Execute the Interrupt service routine
Push the flags into stack.
Clear Interrupt Flag and Trap Flag of the processor.
Push the return address on to the stack.
Load that interrupt vector address in the Program counter / Instruction pointer.
--Execute the Interrupt service routine
ISR bit is reset depending on mode in 8259.

60. Interfacing of 8259 to 8085

61. The PIC 8259 requires 2 addresses with A0 being 0 and 1.
The A0 line from the address bus is connected to the A0 line in 8259.
The higher order address bus is used to select the particular chip by the proper design of the decoder and address.
Read and write control signals of 8085 are connected to the corresponding signals of The data lines of IC8259 are connected to the lower order address and data bus of 8085.

62. The multipurpose SP/EN pin is tied to logic high because only one 8259 is used in the system. The interrupt request line -INT of 8259 is connected to the 8085’s interrupt line INTR. INTA of 8085 is connected to the INTA of 8259.
When only one 8259 is used in a system, the cascade lines (CAS0, CAS1, CAS2) can be left open.
The eight IR inputs of 8259 can be connected to the interrupt sources from different external devices such as A/D converter, keyboard, printer etc.
Unused IR inputs must be tied to ground in order to avoid noise being recognized as interrupt signal.

63. The software part of 8259 intialising involves writing Initialisation command words
After intialisation, the proper operation command words can be written as and when required.