1. YOVI 2008 Core Interrupt Controller (INTC)

2. Features 1. Two interrupt control modes
2. Priorities settable with ICR
3. Three-level interrupt mask control
4. Independent vector addresses
5. Forty-one external interrupts
3. DTC

3. Block Diagram

4. Port Descriptions NMI Input Nonmaskable external interrupt.
Name
I/O
Function
NMI
Input
Nonmaskable external interrupt.
Rising edge or falling edge can be selected
Maskable external interrupts.
Rising edge, falling edge or both edges, or level sensing can be selected individually for each pin.
Pin of IRQn or ExIRQn to input IQR15 to IQR12 interrupts can be selected.
An interrupt is requested at falling edge.

5. Register Descriptions
Interrupt control register A to D (ICRA to ICRD)
Address break control register (ABRKCR)
Break address register A to C (BARA to BARC)
IRQ sense control registers (ISCR16H, ISCR16L, ISCRH,ISCRL)
IRQ enable registers (IER16, IER)
IRQ status registers (ISR16, ISR)
Keyboard matrix interrupt mask registers (KMIMRA, KMIMR6)
Wake-up event interrupt mask register (WUEMR3)

6. Interrupt Control Register A to D (ICRA to ICRD) (1)
The ICR registers set interrupt control levels for interrupts other than NMI
Bit
ICR7
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
ICR0
Initial value
Read/Write
R/W
Interrupt control level
0: Correspongding interrupt source is interrupt control level 0 (no priority)
1: Correspongding interrupt source is interrupt control level 1 (priority)

7. Interrupt Control Register A to D (ICRA to ICRD) (2)
Correspondence between Interrupt Source and ICR

8. Address Break Control Registers (ABRKCR) (1)
Controls the address breaks
An address break is requested, CMF flag = BIE flag = 1

9. Address Break Control Registers (ABRKCR) (2)

10. Break Registers A to C (BARA to BARC) (1)
Specify an address that is to be a break address.
An address in which the first byte of an instruction exists should be set as a break address.
In normal mode, addresses A23 to A16 are not compared

11. Break Registers A to C (BARA to BARC) (2)

12. Break Registers A to C (BARA to BARC) (3)
BARB
BARC

13. IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH,ISCRL) (1)
Select the source that generates an interrupt request
at pins:

14. IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH,ISCRL) (2)

15. IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH,ISCRL) (3)

16. IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH,ISCRL) (4)

17. IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH,ISCRL) (5)

18. IRQ Enable Register (IER16, IER) (1)
Enable or disable of interrupt requests IRQ15 to IRQ0
IER16

19. IRQ Enable Register (IER16, IER) (2)
Enable or disable of interrupt requests IRQ15 to IRQ0
IER

20. IRQ Status Registers (ISR16, ISR) (1)
Are flag registers
Indicate the status IRQ15 to IRQ0 interrupt requests

21. IRQ Status Registers (ISR16, ISR) (2)

22. IRQ Status Registers (ISR16, ISR) (3)

23. (KMIMRA, KMIMR6) (WUEMR3)
Keyboard matrix interrupt mask registers
Wake-up event interrupt mask register
KMIMR and WUEMR
Enable and disable key-sensing interrupt inputs
Wake-up event interrupt inputs

24. KMIMR and WUEMR (2)
KMIMRA

25. KMIMR and WUEMR (3)
KMIMR6

26. KMIMR and WUEMR (4)
WUERM3

27. Interrupt Sources External Interrupts Internal Interrupts
highest-priority
always accepted by
the CPU
requested by an input signal at pins IRQ or ExIRQ15 - 2
requested by an input signal at pins KIN15-0
requested by an input signal at pins WUE15 -8
External Interrupts
NMI Interrupt
IRQ15 to IRQ0 Interrupts
KIN15 to KIN0 Interrupts
WUE15 to WUE8 Interrupts
Internal Interrupts
Fags and enable bits
ICR
DTC
For each on-chip peripheral module
The control level for each interrupt can be set by ICR
The DTC can be activated by an interrupt request from an on-chip
peripheral module.
This activate request is not affected by the interrupt
control mode or the status of the CPU interrupt mask bits.

28. Interrupts IRQ15 to IRQ0

29. Interrupts KIN15 to KIN0

30. Interrupt Control Mode and Interrupt Operation
Interrupt mode 0
Interrupt mode 1
Exception Handling Sequence
Interrupt Response Time

31. Interrupt Control Mode 0
Interrupt Acceptance
Interrupt Control Mode 0

32. State Transition in Interrupt Control Mode 1

33. Interrupt Control Mode 1
Interrupt Acceptant
Interrupt Control Mode 1

34. Interrupt Exception Handling

35. Interrupt Response Time

36. Number of States in Interrupt Handling Routine Execution Status

37. Interrupt Control for DTC

38. Interrupt Source Selection and Clearing Control

39. Thank you!
Q&A