1. ECE 3430 – Intro to Microcomputer Systems
ECE 3430 – Introduction to Microcomputer Systems University of Colorado at Colorado Springs
Lecture #17
Agenda Today
Output Compare
Input Capture and Output Compare Examples
MSP432 Timer_A Review
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

2. Timer Output Compare Function
- Sometimes it is desirable for a microcontroller to generate a precisely-timed digital waveform.
Programmatically driving a waveform by repeatedly forcing a bit high and low
will not yield a digital waveform with good integrity since the CPU can be interrupted at any time!
- Some microcontrollers provide a feature called output compare which can be used to more
accurately produce digital waveforms.
- Our MSP432 provides 5 output compare channels per Timer_A module as part of the
capture/compare timer block.
- Each channel has a dedicated 16-bit output compare register.
- A 16-bit value is loaded into the output compare registers. When TAR is equal to this value,
an internal event is triggered.
- When this internal event is triggered the output compare circuitry will alter the value on an
output pin. These output pins can be associated with MSP432 external I/O pins (see device
specific datasheet).
- The output of each channel is called OUTx (OUT0, OUT1, …, OUT4).
- In all cases, PxDIR.x must be 1 (to make the I/O pin an output) and PxSEL0.x and PxSEL1.x
must be adjusted to disconnect the output from the normal CPU-controlled, general-purpose
I/O and connect it to the timer (device-specific datasheet has the details).
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

3. Timer Output Compare Function
Output Compare Details - When the output compare generates an internal event (when the TACCRx register and
TAR match), the OUTMODx bits in the TACCTLx register specify what to do
to the respective output pin:
Mode Bit Bit 6 Bit Output value in OUT bit (in TACCTLx as well) Set Toggle/reset Set/reset
Toggle
Reset
Toggle/set
Reset/set NOTES: * Modes 2, 3, 6, and 7 are only useful in up and up/down TAR count modes.
* These modes are not useful for channel 0—since TACCR0 is used as the count
threshold in up and up/down modes.
* The first action is taken when TAR = TACCR1 and the second when TAR=TACCR0+1.
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

4. Timer Output Compare Function
Output Compare Details - The 16-bit output compare registers for each of the output compare channels are: Output Compare Channel 0 = TACCR0
Output Compare Channel x = TACCRx
- During output compare function, these registers are treated read/write by software!
- When the TAR and TACCRx registers match, a “flag bit” (CCIFG) will be set in the
appropriate TACCTLx register This flag only indicates that the registers matched and action has been taken on the
associated output pin. It is set even if interrupts are disabled.
- These flags can be cleared by writing a ‘0’ to the corresponding flag bit: CCIFG = 0 = flag cleared, waiting for output compare event (RESET state) CCIFG = 1 = flag set, output compare event occurred sometime in the past
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

5. Timer Output Compare Function
Output Compare Function (Optional Interrupt)
(all of this is the same as it was for input capture)
- Just as with the timer overflow, the flag getting set when action is taken
against an output pin can generate an interrupt—however this is not a requirement!
- Just like all MSP432 interrupts, each output compare channel has a relative priority. Output compare
channel 0 has a higher priority than all the other output compare channels (see interrupt
vector table in device-specific datasheet).
- The timer overflow and compare channel 1-4 interrupts share an interrupt vector, so the source
of the interrupt must be determined. The TAIV register can be used to do this expediently.
TAIV is set to a distinct value based on the highest-priority, pending timer interrupt. The associated
flag is automatically cleared by hardware.
- Just like many other MSP432 interrupts, there is both a global and local interrupt mask involved:
Global mask = I flag in the PRIMASK (this is a maskable interrupt) -> OK for CPU to accept Local mask = CCIE bit in appropriate TACCTLx register -> OK for timer to generate
NVIC mask = NVIC_ISERx register bit to pass from the Timer_A module into the CPU.
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

6. Timer Output Compare Function
Output Compare Details - The CAP bit in the TACCTLx register must be set to 0 for compare mode—it is set
to 1 only when the timer channel is used in input capture mode.
- The OUT bit in the TACCTLx register can be set to force the timer-controlled output to
either digital value (0 or 1)—provided the OUTMOD bits are all 0. This allows software to take
control of the output pin at times if required.
- Attempting to change the state of port pins under the control of an output compare channel
using PxOUT will have no effect! The general-purpose port logic is disconnected from the
output pin!
- If trying to generate a periodic waveform by actively changing the TACCRx register in an
ISR, the ISR must complete before TAR matches the new value of TACCRx. This would
happen if you try to generate an arbitrarily high-frequency waveform. The CPU speed puts
a limitation on the attainable frequency in this situation.
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

7. Timer Output Compare Function
Output Compare Applications Generate Square Waves - A square wave with a pre-defined duty cycle and frequency
(period) can be generated. Useful in PWM control (motors) Generate Fixed Delay after Event When an event occurs, we can trigger a specific # of “counts” after the event. Could also be an accurate delay subroutine Generate a Pulse with a Certain Width Trigger two ‘toggle’ output compares a certain  count between edges.
Event
Output Compare
 TCNT 
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

8. Timer Output Compare Function (Example)
Output Compare Example Generate a square wave with a pulse width equal to TAR rollover on P2.4 (OUT1).
P2.4 is associated with Timer_A instance 0, channel 1.
* Need to set P2.4 as an output and to use alternate function (timer-controlled).
* Need to tell compare channel to toggle output.
* Need to set up TAR in continuous count mode (sourced from SMCLK).
* Can optionally enable interrupts (for CPU notification) and provide ISR.
Because we could configure the count threshold (by setting TA0CCR0 and switching
to “up” TAR count mode), we can control the frequency of the 50% duty cycle waveform.
We could also use “up” or “up/down” TAR count mode in combination with TA0CCR1 to create a
waveform with a non-50% duty cycle.
Roll Over
Roll Over
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

9. Timer Output Compare Function (Example)
Output Compare Example Cont… //
// Set up P2.4 to generate a waveform through TA0.1
void EnableWaveform() {
// Set up output pin parameters
P2DIR |= BIT4; // P2.4 is output
P2SEL0 |= BIT4; // Multiplexing
P2SEL1 &= ~BIT4; // " "
// Set up attributes for TimerA instance 0
// (common to all channels)
TA0CTL = (TASSEL_2 | ID_0 | MC_2); // SMCLK sourced, /1, “continuous" mode, no interrupts
// Set up the channel-specific functions (for channel 1)
TA0CCTL1 = OUTMOD_4; // toggle output pin }
int main(void)
EnableWaveform();
// CPU can now do other things here or go to sleep. The Timer_A module is creating a precisely-timed waveform
// all by itself. Any low power modes entered must keep the clocks alive however.
return 0;
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

10. Timer Input Capture Function (Example)
Input Capture Example Measure the frequency of a digital waveform provided on P2.4:
P2.4 is associated with Timer_A instance 0, channel 1.
* Need to set P2.4 as an input and to use alternate function (routed to timer block).
* Need to tell capture channel to look for rising (or falling edges). Both is overkill.
* Need to set up TAR in continuous count mode (sourced from SMCLK).
* Can optionally enable capture interrupts (for CPU notification) and provide ISR.
The captured TAR value will be in TA0CCR1 when the edge occurs. If we wanted to measure
duty cycle too, we would need to look for both edges. For period/frequency only, either
edge (but not both) would be sufficient.
Period
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

11. Timer Input Capture Function (Example)
Input Capture Example Cont…
// Function prototype
extern void EnableInterrupts(void); // defined in startup_msp432.s
void SetupPeriodMeas() {
// Set up output pin parameters
P2DIR &= ~BIT4; // P2.4 is input
P2SEL0 |= BIT4; // Multiplexing
P2SEL1 &= ~BIT4; // " "
// Set up attributes for TimerA instance 0
// (common to all channels)
TA0CTL = (TASSEL_2 | ID_0 | MC_2); // SMCLK sourced, /1, "continuous" mode, no interrupts
// Set up the channel-specific functions (for channel 1)
// - configure input capture channel 1 (rising edges)
// - sourced by CCI1A
// - interrupt notification on capture
TA0CCTL1 = (CM_1 | CCIS_0 | SCS | CAP | CCIE);
// Allow interrupt to pass through NVIC
NVIC_ISER0 |= BIT9;
// Allow maskable interrupts into the CPU
EnableInterrupts(); }
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

12. Timer Input Capture Function (Example)
Input Capture Example Cont…
// Global variables (shared between main and ISR)
volatile unsigned short period;
volatile unsigned short prevCap;
void TA0_N_IRQHandler(void) {
// read TA0CCR1 to prevent COV flag,
// pull into a local variable
unsigned short curCap = TA0CCR1;
// update global variables
period = curCap - prevCap;
prevCap = curCap;
// clear the CCIFG flag in the TA0CCTL1 before returning
TA0CCTL1 &= ~CCIFG; }
int main(void)
SetupPeriodMeas();
// Timer_A module is capturing times and calling the ISR above. Whenever the CPU wants, it can access
// the “period” global variable above…
float freq;
freq = (float)1/period;
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

13. ECE 3430 – Intro to Microcomputer Systems
Timer Review
MSP432 Timer_A block
Our MSP432 has 4, 5-channel Timer_A modules. They are referred to as Timerx_An (where
x is the instance number and n is the number of channels. Each Timer_A register is annotated
with the Timer_A module instance number (required if not using instance 0).
Ex) TA0R = TAR = timer register for Timer0_A5 TA1R = timer register for Timer1_A5
TA0CCR1 = TACCR1 = capture/compare for instance 0, channel 1.
TA1CCR2 = capture/compare for instance 1, channel 2.
Main Timer - A 16-bit counter (TAR) that runs off of an internal or external clock source. It can trigger
an interrupt upon overflow (return to 0x0000). The speed of the counter can be
clocked down by a factor of 2, 4, or 8. The maximum count value can be established
via a register (TACCR0). The counter can count in up/down mode.
Input Capture – Used to capture external events via dedicated input pins. When the event occurs, the value of TAR is loaded into a pre-defined register (TACCRx). This is then used to calculate relative timing information between events. This can also cause an interrupt.
Output Compare - Compare registers (TACCRx) are loaded with a 16-bit values. When TAR reaches the value in the register, an output compare trigger will occur. Upon the compare event, output pins on the MSP432 can be altered. This can also cause an interrupt.
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

14. ECE 3430 – Intro to Microcomputer Systems
Timer Review
The channel 0 capture/compare register (TACCR0) serves an alternate purpose when the TAR
is counting in “up” or “up/down” mode and, hence, cannot be used for typical compare/capture
purposes in that scenario. If the TACCR0 is not needed to specify a threshold for this TAR count
mode, it can be used for capture/compare purposes.
All channels within a Timer_A instance share a common timer block (TAR). Independent Timer_A
instances can be configured independently with potentially different clock domains.
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

15. ECE 3430 – Intro to Microcomputer Systems
Timer Review
The Timer_A peripheral registers are:
TACCR0: Serves as count threshold in “up” and “up/down” mode—otherwise a typical compare or
capture register for channel 0.
TACCRx: Capture/compare register for channel x. Software reads this during input capture and
writes this during output compare.
TAR: The main timer (a 16-bit counter). Readable and writeable by software—but typically not
modified by software.
TACTL: The Timer_A “timer block” control register. Used to set up all the parameters of the
“timer sub-block”. Does not specify the behavior of capture/compare timer blocks.
TAIV: The Timer_A “interrupt vector generator”. An optional mechanism that expedites handling
of timer interrupts (when more than one possible source is involved). This is a “reactive”
register in that hardware state will change as a result of reading it (flags are cleared).
TACCTLx: The channel x capture/compare configuration register. All input capture and
output compare parameters are specified here.
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015

16. ECE 3430 – Intro to Microcomputer Systems
Timer Review
The main timer (TAR) is normally left in continuous count mode for input
capture. Specifying a roll-over threshold other than 0xFFFF can complicate
math in some situations. Allowing the timer to run backwards further
complicates things. These alternate count modes are more useful for
output compare.
The “up” and “up/down” count modes for TAR add much flexibility to the output
compare system when generating a waveform. The combination of TAR clock
source, TAR clock pre-scalar, and threshold allow tight control over the
frequency of TAIFG (timer overflow events).
The additional count modes also make changing the frequency or duty cycle
of the output waveform (when using output compare) much easier. Generating
periodic waveforms does not need to require periodic interrupts (and CPU
servicing) thanks to these flexible count modes.
Lecture #17
ECE 3430 – Intro to Microcomputer Systems
Fall 2015