1. ENG2410 Digital Design “CMOS Technology”
Fall 2017
S. Areibi
School of Engineering
University of Guelph

2. The Transistor Revolution
Intel 4004 processor
Designed in 1971
Almost 3000 transistors
Speed:1 MHz operation
Bipolar logic
1960’s
First transistor
Bell Labs, 1948

3. Transistors Can be classified as: BJT – Bipolar Junction Transistor;
Bipolar device (two carriers)
Current controlled device
FET – Field Effect Transistor;
Unipolar device (single carrier)
Voltage controlled device

4. Logic Families RTL, DTL earliest TTL was used 70s, 80s CMOS
Still available and used occasionally
7400 series logic, refined over generations
CMOS
Was low speed, low noise
Now fast and is most common
BiCMOS and GaAs
Speed

5. CMOS Technology

6. Semiconductor Materials
Electronic materials generally can be divided into three categories:
Insulators
Semiconductors
Conductors
The primary parameter used to distinguish among these materials is the resistivity (rho)
Insulator < rho
Semiconductors 10-3 < rho < 105
Conductors rho < 10-3
Silicon and germanium are the most important semiconductor materials

7. P-type and N-type
The real advantage of semiconductors emerge when impurities are added to the material in minute amounts (Doping)
Impurity doping enables us to change the resistivity over a very wide range and determine whether the electron or hole population controls the resistivity of the material.
Donor Impurities: have five valence electrons in the outer shell (phosphorus and arsenic). Semiconductors doped with donor impurities are called n-type.
Acceptor Impurities: have one less electron than silicon in the outer shell (boron). Semiconductors doped with acceptor impurities are known as p-type.

8. Field Effect Transistor
MOSFET: Metal Oxide
Semiconductor
Field Effect Transistor
A voltage controlled device
Dissipates less power
Achieves higher density on an IC
Has full swing voltage 0  5V

9. The MOS Transistor
Polysilicon
Aluminum

10. nMOS Transistor |V GS |
An nMOS Transistor
Ids
Vgs

11. Transistor as a Switch
A Switch! |V GS |
An MOS Transistor

12. Implementing Logic using: nMOS vs. pMOS Devices

13. CMOS:Complementary MOS
Means we are using both N-channel and P-channel type enhancement mode Field Effect Transistors (FETs).
Why?

14. Threshold Drops VDD VDD PUN VDD 0  VDD 0  VDD - VTn VGS CL CL
EE141
Threshold Drops
VDD
VDD
PUN S D
VDD
Strong ‘1’
Weak ‘1’ D S
0  VDD
0  VDD - VTn
VGS CL CL
VDD  0
PDN CL
VDD
VDD  |VTp| S D
VGS
Why PMOS in PUN and NMOS in PDN … threshold drop
NMOS transistors produce strong zeros; PMOS transistors generate strong ones
Strong ‘0’
Weak ‘0’

15. Complementary MOS (CMOS)
NMOS Transistors pass a ``strong” 0 but a ``weak” 1
PMOS Transistors pass a ``strong” 1 but a ``weak” 0
Combining both would lead to circuits that can pass strong 0’s and strong 1’s X Y C
School of Engineering

16. Complementary MOS (CMOS)
VDD
PUN and PDN are dual logic networks
In1
PMOS only
In2
PUN …
InN
F(In1,In2,…InN)
In1
In2
PDN …
NMOS only
InN
VSS
One and only one of the networks (PUN or PDN) is conducting in steady state
At every point in time (except during the switching transients) each gate output is connected to either VDD or VSS via a low resistive path
School of Engineering

17. CMOS Inverter
Pull-up Network A Y 1
Pull-down Network

18. CMOS Inverter A Y 1

19. CMOS Inverter A Y 1

20. CMOS Tri-State InverterY X Z 1 E Y E

21. NMOS Transistors in Series/Parallel Connection
EE141
NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high

22. PMOS Transistors in Series/Parallel Connection
EE141
PMOS Transistors in Series/Parallel Connection

23. Example Gate: NAND
School of Engineering

24. Example Gate: NOR
School of Engineering

25. Construction of Compound Gates
Example:
Step 1 (n-network): Invert F to derive n-network
Step 2 (n-network): Make connections of transistors:
AND  Series connection (A.B) …. (C.D)
OR  Parallel connection ((A.B) + (C.D))

26. Construction of Compound Gates
Example:
Step 1 (n-network): Invert F to derive n-network
Step 2 (n-network): Make connections of transistors:
AND  Series connection (A.B) series, (C.D) also in series
OR  Parallel connection ((A.B) + (C.D)) in parallel

27. Construction of Compound Gates (cont’d)
Step 3 (p-network): Expand F to derive p-network
each input is inverted
Step 4 (p-network): Make connections of transistors (same as Step 2).

28. Construction of Compound Gates (cont’d)
Step 3 (p-network): Expand F to derive p-network
each input is inverted
Step 4 (p-network): Make connections of transistors (same as Step 2).
Step 5: Connect the n-network to GND (typically, 0V) and the p-network to VDD (5V, 3.3V, or 2.5V, etc).

29. Complex CMOS Gate D A B C OUT = D + A • (B + C) D A B C
Shown synthesis of pull up from pull down structure
School of Engineering

30. CMOS Properties
There is always a path from one supply (VDD or GND) to the output.
There is never a path from one supply to the other. (This is the basis for the low power dissipation in CMOS—virtually no static power dissipation.)
There is a momentary drain of current (and thus power consumption) when the gate switches from one state to another.
Thus, CMOS circuits have dynamic power dissipation.
The amount of power depends on the switching frequency.

31. End Slides