1. Ultra-Low-Voltage UWB Baseband Processor
Objective: Demonstrate ultra-low-voltage operation for high performance applications
Possible Applications: Communication or signal processing in energy constrained environment
Target Example: UWB radios on battery operated devices. Need to reduce energy consumption.
Challenge: Minimize energy consumption while meeting throughput constraint of 500-MSPS for 100-Mbps data rate
Approach: Extreme parallelism in the digital baseband processor of the UWB receiver
Sampling Rate
500 MSPS
Data Rate
100 Mbps

2. Proposed Parallelized Architecture
Improve energy-efficiency by exploiting TWO forms of extreme parallelism in the correlator in baseband processor
Ultra-Low-Voltage Operation: Maintain Throughput (20x)
Reduce supply voltage
Minimize energy of baseband processor
Reduce Acquisition Time: Parallelized Computation (31x)
Reduce receiver on-time
Minimize energy of entire receiver
620 correlators

3. Results and Performance Summary
Minimum Energy Point
Total Energy
Dynamic Energy
Leakage Energy
3.3 mm
ST 90-nm CMOS
281,260 gates V
Reduced baseband energy by 6x
Acquisition Energy
Reduce RF front-end and ADC energy!
14X overall
reduction
Reduced receiver energy by 14x
Baseband consumes 2 mW [20 pJ/bit] for a 4-kbit packet
Lowest reported energy per bit!
Acknowledgments: DARPA and NSERC Fellowship for funding