1. Cadence Low-Power Solution

2. Common Power Format (CPF) Helps Integrate the Power Intent Across the Entire Flow
Logic is “Connected”
Power is “Connected”
Formal
Analysis
Testbench
Simulation
Parser
Hardware
Parser
Formal
Analysis
Testbench
Simulation
Hardware
Parser
Parser
Parser
Parser
Management
Synthesis
Management
Synthesis
Parser
Parser
Parser
Parser
Logic Information
(Verilog)
Power Information
(CPF)
SVP
Equivalence
Checking
SVP
Equivalence
Checking
Parser
Parser
Parser
Parser
Parser
Test
Parser
Test
P+R
Parser
P+R
Parser IP
Libraries IP
Libraries
Can be Automated
Can be Automated
September 19, 2018

3. A Common Power Format Communicates the Power Intent Throughout the Flow
Common Power Format (CPF) = Single specification of power intent used throughout Design, Verification, and Implementation
ASCII file that captures:
Power design intent
Power domain
Logical: hierarchical modules as domain members
Physical: power/ground nets and connectivity
Analysis view: timing library sets for power domains
Power logic
Level shifter logic
Isolation logic
State-retention logic
Switch logic & control signals
Power modes
Definitions
Transition expressions
Modal analysis
Technology information
Level shifter cells
Isolation cells
State-retention cells
Switch cells
Always-on cells
The Common Power Format is a new single specification of power intent for use throughout the design chain. It is a standard, ASCII file that specifies the information listed here. You can see that the information spans design and implementation, including library information. Finally it is important to note the power constructs that will require functional verification – isolation, state retention, switch and control signals, and power modes.
September 19, 2018

4. The Cadence Low-Power Solution
Low Power Functional Verification
Low Power Functional Verification
Static Timing Analysis
SI & Static Timing Analysis
Power Estimation
Power Estimation
Logic Verification Management
Logic Verification Management
Timing/Power/Area Optimization
Timing/Power/Area Optimization
Low Power Implementation
SoC Encounter
Low Power Logic Verification
Incisive IES
Low Power Logic Verification
Low Power Logic Verification
Top-down MSV/PSO
Single-pass Synthesis
Top-down MSV/PSO
Single-pass Synthesis
Design for Test
Design for Test
Low Power Verification
Conformal-LP
Power Analysis
Power Analysis
Low Power Synthesis
RTL Compiler
Silicon Virtual Prototype
Silicon Virtual Prototype
Placement including
SRPG/Level shifters/Isol. cells
Placement including
SRPG/Level shifters/Isol. cells
Low Power
Clock Tree Synthesis
Low Power
Clock Tree Synthesis
Signoff Power Analysis Voltagestorm
Domain Aware NanoRoute
Domain Aware NanoRoute
Low Power DFT Encounter Test
IR-Aware Timing/SI Opt.
IR-Aware Timing/SI Opt.
Decap insertion
Decap insertion
Sign-off
Sign-off
MSV Infrastructure
September 19, 2018