1. Customer Presentation
ASIC Replacement FPGAs
ASIC Features
ASIC Pricing
Immediate Production HDL Design Flow
FPGA Flexibility at ASIC Prices!
Customer Presentation

2. Spartan FPGAs Replace Gate Arrays in Production
Agenda
Spartan Highlights
Advantages vs. Gate Arrays
Spartan Alternative to ASIC Conversions
Spartan Replaces Obsolete Gate Arrays

3. Highlights

4. How are Spartan FPGAs Different
How are Spartan FPGAs Different? Spartan Matches Gate Array Die Size & Cost
FPGAs compete
FPGAs are Fab process drivers, replace DRAMs
Competitive die size with similar number of I/O
FPGAs cannot compete with gate arrays
Older process than ASICs
Larger die
Not I/O pad limited
1995
1998
FPGA
1.0u, 5K gates
Gate Array
0.8u, 10K gates
SpartanXL,
0.35u, 10K gates
Gate array,
0.35u, 100K gates
160 I/O
160 I/O
160 I/O
160 I/O

5. Performance, RAM, Cores, and Low Price
Xilinx Spartan Series
5 Volt -> 0.5/0.35µ XCS05 XCS10 XCS20 XCS30 XCS40
3 Volt -> 0.35/0.25µ XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL
System Gates 2K-5K 3K-10K 7K-20K 10K-30K 13K-40K
Logic Cells
Max Logic Gates 3,000 5,000 10,000 13,000 20,000
Flip-Flops
Max RAM bits 3,200 6,272 12,800 18,432 25,088
Max I/O
Performance 80MHz 80MHz 80MHz 80MHz 80MHz
No Compromises:
Performance, RAM, Cores, and Low Price

6. Spartan Features: On-chip SelectRAM™
> 75% ASIC designs need RAM *
SelectRAM advantages:
Dual Port Synchronous
Higher speed (to 100 MHz) than RAM compilers
More flexible - numerous distributed small RAMs
* Source: Dataquest

7. Spartan Extensive Core Support
Spartan Core Advantages:
Pre-verified in silicon
Much lower cost than ASIC cores
Simple distribution and licensing
Communications & Networking Products Asynchronous Transfer Mode Forward Error Correction Base-Level Products Basic Elements Math Functions RISC CPU Cores 8-bit RISC core Processor Peripherals UARTs Others
Standard Bus Interface Products
Peripheral Component Interconnect Bus (PCI)
Other Standard Bus Products
Digital Signal Processing
Correlators
Filters
Transforms
DSP Building Blocks

8. Spartan FPGAs Designed for Low Price
Smallest die of any FPGA with RAM
Focused package offering
Streamlined test process
Optimized production flow
High-volume pricing < $3.00*
* 100K units
84PLCC, -3 speed

9. Spartan Price Reductions Thru Technology
5V Price* 3V Price**
XCS05 $3.95 $3.50 XCS05XL $2.95
XCS10 $5.50 $4.80 XCS10XL $3.95
XCS20 $6.50 $6.50 XCS20XL $5.45
XCS30 $7.95 $7.95 XCS30XL $6.95
XCS40 $ $13.80 XCS40XL $9.90
NEW
* 100K units, end ** 100K units, mid 1999
Cheapest pkg, slowest speed Cheapest pkg, slowest speed

10. Cost Effective Cores Replaces Standard Devices
XCS30XL
Price
Percentage of
Device Used
Effective
Function Cost
Core Function
UART
$6.95
17%
$1.20
16-bit RISC Processor
$6.95
36%
$2.60
16-bit, 16-tap
Symmetrical FIR Filter
$6.95
27%
$1.90
Reed-Solomon
Encoder
$6.95 6%
$0.45
PCI Interface
(in PQ208)
$8.25
45%
$3.80

11. Spartan Cost Reduction Roadmap
Without Compromises
ASIC prices
Increased density & speed
More SelectRAMTM
Added cores
Spartan
$395*
SpartanXL
$295*
0.5 3LM
5 Volt
Spartan-II
$200*
Price
0.35 5LM
Spartan-III
$150*
3.3 Volt
0.25 5LM
0.2
2.5 Volt
1.8 Volt
2002
* Prices are per 5K system gates,
100K units, slowest speed, 84-PLCC

12. Advantages
vs. Gate Arrays

13. Spartan Replaces Low-Density Gate Arrays
Gates : I/O Fit
120
100 80 60 40 20 10
Gate Array Territory
High Density,
Low I/O
1999
System Gates
Spartan II
1998
S40
S30
Spartan I
S20
Spartan FPGAs
Low Density,
High I/O
S05
S10 50
100
150
200
250
300
I/O’s

14. “Out-the-Door” Costs are Higher! = $$$
Costs of ASIC Design
Like Buying a New Car
New Car Purchase --
Expected Costs:
MSRP* $$$
Hidden costs:
Dealer rebates/ holdbacks..
And Unexpected costs:
Dealer prep, destination charges, rustproofing ….
“Out-the-Door” Costs are Higher! = $$$
* Manufacturer’s Suggested Resale Price

15. Spartan Avoids Expected Costs

16. Spartan Avoids Unexpected Costs

17. Spartan Avoids Hidden Costs

18. Gate Array Cost Worksheet - New Designs
Gate Array Cost* Typical Range Customer Costs FPGA
Expected costs:
NRE cost $15-20K ______________ None
ATPG from outside service/insert scan 10-20K ______________ None
Higher cost of ASIC cores K ______________ 50-70% less
Generate & debug testbench 10-20K ______________ None
Unexpected costs:
Silicon design iteration
(needed in 33-50% of ASIC designs) K ______________ None
Extensive customer sign-off (temp, V, MHz sim) 10-20K ______________ None
Expedite prototype/production
(hot lot, risk mask, rush assembly) 10-40K ______________ None
Large $ commitment
(MOQ, min ship qty, ties up cash) 50K+ ______________ None
Demand slackens (obsolete stock) 10-20K ______________ None
Hidden costs:
ASIC production leadtimes (8-10 wks;
lost sales, delayed market entry) 25K+ ______________ None
Design change needed in production 20K ______________ None
Scrap obsolete inventory 20-30K ______________ None
Conversion to ASIC costs/risks 20K+ ______________ None
Large ASIC inventory-carrying cost 5-15K ______________ None
Stock multiple ASIC codes:
(FPGA single bin stocking) 15-20K ______________ None
Difficult JIT delivery/supply chain management 10K+ ______________ None
Total Gate Array Costs - New Designs $50K-150K ______________ None
* Assumption: Engineering $10K man/mo

19. Design
Flows

20. Converging Methodologies
Design
Productivity
FPGAs close the design gap
Behavioral & IP
Behavioral & IP
ASIC
Methodology
Verilog , VHDL
Verilog , VHDL
Gates
RTL
Gates
Gap
FPGA
Methodology
Schematic
Transistors
Transistors
Boolean equations
1980
1985
1990
1995
2000
Year

21. Gate Array Design Flow FPGA flow is similar, but:
ASIC
FPGA flow is similar, but:
SCAN /test vectors not needed for low densities
Built-in JTAG
Make mistakes, no penalty
Concurrent engineering
Real-time verification
Functional
simulation
VHDL/Verilog
Insert Scan
Synthesis
Create
test vectors
Simulation
ASIC vendor
Place & Route
Not needed
with FPGAs
Static timing
Customer quote:
“FPGAs – I love being able to make mistakes. I can relax and I don’t have to simulate as much. It’s in my control.
ASICs – We sweat and don’t sleep much until the ASIC is available and tested.” ”
Sign-off
ECO
Fab prototype
4 wk Lead-time
Initial production
8-10 wk Lead-time
Volume
Production

22. Spartan Supports Gate Array Tools
Synopsys, Cadence, Mentor, Viewlogic
93% of gate array designers use Synopsys
Support of industry standards
EDIF, VITAL, VHDL, Verilog, SDF
Vendor
Simulation
Synthesis
Schematic
Other
Synopsys
VSS
FPGA Express
DesignWare
Vital Sim Models
FPGA Compiler II
Motive static timing
Design Compiler
Cadence
Verilog XL
Synergy
Concept
Mentor
MTI ModelSim
Falcon Framework
V-System
Viewlogic
Viewsim
WorkView

23. Spartan FPGA Highlights
Spartan Replaces Gate Arrays
 Up to 40K system gates, 224 I/O
Spartan Meets ASIC Requirements
Performance to 80MHz
On-chip RAM
Silicon-verified Cores
Aggressive volume prices
Spartan FPGAs Avoid ASIC Costs
Expected costs: NRE, scan, test vectors, ….
Hidden costs: Leadtimes, inventory design changes, …
Unexpected costs: Spins, sign-off, expediting, ..
HDL Design Flow with Broad 3rd Party Support
Synopsys, Cadence, Mentor, MTI, Synplicity, Exemplar , ….
ASIC Barriers

24. FPGA-to-ASIC
Conversion

25. FPGA Cost-Reduction Paths
FPGA-to-ASIC Conversion
Costly
Path
ASIC
FPGA
Direct Translation or Retarget:
Engineering costs,
Conversion/ NRE fees,
4 month leadtime-to-production, design risks
New
Paradigm
Spartan FPGA into Production
No added engineering effort, no NREs,
Cost reductions through Spartan II, III, ….
Full production NOW!

26. Advantages of FPGAs in Production
Spartan Avoids ASIC Migration Costs & Lead-times
ASIC NRE/ Conversion fees
Typical range of $5-25K
Customer engineering costs:
Verify new gate array design
Simulation, test program, sign-off
Characterize/ qualify new prototypes
Delay work on next project
Lead-times for conversion-to-production a best case of 4 months
Conversion time 3 weeks, proto 3 weeks,
production 10 weeks = 4 months
What is the product life? Is there a mid-life update?

27. Spartan Advantage No Unexpected Re-design Risks
Result
Design relies on FPGA
Features not found on ASIC
features
Example: JTAG, on-chip RAM,
global reset, LogiCORE,...
Netlist is modified
Often must be modified to add functions
Buffers and clocks are adjusted to optimize drive capability
Timing issues
Asynchronous timing
Gated clocks
Porting CORES
Timing changes between ASIC/
FPGA
Complex licensing issues
Xilinx / Alliance cores are not
transferable
Any mistake will exist in final ASIC

28. Gate Array Cost Worksheet - FPGA-to-ASIC Conversion
FPGA Conversion Costs* Potential Impact Actual FPGA Costs
Expected costs:
NRE/conversion fees $15-30K ______________ None
Verify re-design (sim, vectors, & prototypes) Engineer’s time ______________ None
Insert JTAG Engineer’s time ______________ None
Higher cost of ASIC cores K ______________ 50-70% less
Unexpected costs:
4 months conversion-to-production time Higher volume ______________ None
Conversion - 3 weeks needed to
Prototype - 3 weeks break even
Production delivery - 10 weeks
Total time = 16 weeks
Hidden costs:
Lose reprogrammability advantage More costly changes/
No field updates ______________ None
Scrap obsolete inventory if design changes 20K ______________ None
Higher inventory costs/levels 10K ______________ None
Conversion re-design risks:
Converting FPGA features
(RAM, JTAG, reset) Not work in-system ______________ None
Modify netlist - new buffers/
new drive capability Not work in-system ______________ None
Device timing changes Not work in-system ______________ None
Porting of FPGA Cores Difficult licensing ______________ None
Total ASIC Costs/Impact - Conversions $50K-100K+ ______________ None
* Assumption: Engineering $10K man/mo

29. FPGA-to-ASIC Conversion The New Paradigm: FPGAs in Production
New paradigm - Spartan FPGAs in production
Spartan proto to production retains FPGA flexibility
Faster, less costly transition to volume production
Cost reduction path with future Spartan Series
Spartan II in 1999
Spartan III TBA
Spartan avoids redesign costs to gate array
Conversion fees
Added customer engineering
Long-lead-times for production
Eliminates unexpected migration design risks
FPGA features difficult to emulate
Net list changes

30. Obsolete
Gate Arrays

31. Leading Suppliers Exit Gate Arrays
Deep sub-micron process increases mask and wafer costs
Accelerates pace to shut down older processes
LSI & Motorola obsolete Gate Array families
No new Gate Array since 1995
Exited Gate Array in 1996,
FPGA in 1998
LL7000 Series (2.0m to 10K gates)
LL8000 Series (2.0m)
LCA Compacted Array
(to 50K gates)
HDC Series (1.0m)
H4C Series (0.8m)
H4CPlus Series (0.65m)
H4EPlus Series (0.65m)
M5C Series (0.5m)

32. Example Flow Converting Obsolete ASICs to an FPGA
RFQ
Package
Quote
Package
Design
Validation
Production
Specifications
Design files
Timing Diagrams
Package Rqmts.
Quality Stds.
Operating Cond.
Interface Rqmts.
Quantity
Schedule
Review RFQ Pkg.
Business
Technical
Prepare Quote:
Price
Delivery
Design Reviews
Terms
Deliverables
Responsibilities
Create Design
Simulate
Debug
Modify
Test Vectors
Documentation
Verify Design
Verify Functionality
System Test
System Debug
Verify Test Vectors
Materials from:
Insight
Memec ICG
Contract
Customer
Responsibility
Memec
Responsibility
Source: Memec Design Services

33. Obsolete ASIC to Spartan FPGA “Made Easy”
Leading suppliers exit gate arrays
Increasing gate array costs
LSI Logic and Motorola
Spartan provides low-cost production solution
Add/delete features, integrate logic
Update design files to Verilog or VHDL for maintainability
Long term stable supply
No mask charges
Xilinx Certified Design Centers have conversion experience
Design centers can provide turnkey service
Insight - Memec Design Services
Avnet - Design Services

34. Spartan FPGAs Displace Gate Arrays In Production
ASIC Barriers
Spartan meets ASIC requirements
ASIC features, pre-verified COREs, aggressive prices, avoids costs of ASIC design and enables flexible production
Supports HDL tools and methodology
Broad 3rd party support, flexible design-flow
Provides effective production cost-reduction path
Avoids costs and risks of redesign to gate array
Obsolete gate arrays convert to Spartan FPGAs
Majors exit gate arrays
Conversion to Spartan made easy by Xilinx Design Centers

35. ASIC Replacement
Addendum

36. Spartan Tool Alternatives
ASIC Tools
ASIC design tool:
Synopsys Design Compiler
Synopsys HDL synthesis (93% of designs)
VHDL/ Verilog = 50% shares
Synopsys Test Compiler
Scan insertion
Generate test vectors
Increases die size/ impacts performance
Spartan Tools
FPGA Alternative:
Synopsys FPGA Express
& FPGA Compiler II
Synplicity, Exemplar
New scripts needed
Test Compiler Not Needed
Scan is not needed by FPGA
100% factory tested
Test vectors are optional

37. Spartan Tool Alternatives
ASIC Tools
ASIC design tool:
RAM compiler
Expands used gates
Lower performance RAM
HDL simulators
Cadence VerilogXL
MTI, more….
Static timing
Quad Motive
Synopsys Primetime
Cores
In-house
3rd Party
Spartan Tools
FPGA Alternative:
Xilinx compiler
On-chip SelectRAM
No performance impact
HDL simulators
Cadence VerilogXL
MTI, more …..
Static timing
Quad Tier 1 in Alliance 2.1
Xilinx Static Timing
Cores
LogiCORE
AllianceCORE

38. There Are Design Methodology Differences
HDLs were developed for ASICs
Achieving 66MHz speed with ASIC is easy
FPGAs require more structured techniques
FPGA design optimization requires architectural “know-how”
Complex functions operate > 50MHz
Critical design technique is pipelining
FPGA offer freedom to do design, not under gun till working parts

39. Extensive Core Support for Spartan Partial list of Spartan Cores
Communications & Networking Products Asynchronous Transfer Mode CRC10 Generator and Verifier (CC-130) CRC32 Generator and Verifier (CC-131) Forward Error Correction Reed-Solomon Decoder Reed-Solomon Encoder Viterbi Decoder Base-Level Products Basic Elements Constant Two Input Multiplexer Three Input Multiplexer Math Functions 1's and 2's Complement Accumulator Scaled by 1/2 Accumulator Registered Adder Registered Loadable Adder Registered Scaled Adder UARTs XF-8250 Asynchronous Communications Element M16450 Universal Asynchronous Receiver/Transmitter Processor Peripherals C2910a Microprogram Controller M8254 Programmable Timer M8255 Programmable Peripheral Interface
Partial list of Spartan Cores
Peripheral Component Interconnect Bus (PCI)
PCI32 Spartan Master & Slave Interfaces
Other Standard Bus Products
IIC
Digital Signal Processing
Correlators
One Dimensional RAM Based Correlator
One Dimensional ROM Based Correlator
Filters
Comb Filter
16-Tap, 8-Bit FIR Filter
Serial Distributed Arithmetic FIR Filter
Dual Channel Serial Distributor Arithmetic FIR Filter
Parallel Distributed Arithmetic FIR Filter
Transforms
DFT Core, (Real Data In, Complex Data Out)
FFT Core, (1024 Points)
DSP Building Blocks
SDA FIR Control Logic
Sine/Cosine
Processor Products
RISC CPU Cores

40. Spartan FPGA Comparison vs. Gate Arrays
Design: Spartan Gate Array
Test vectors/ ATPG None Long
Prototyping time Hours Weeks
Silicon design change Hours Weeks
Cost of iterations None High
Cost of CORES Low High
Production:
Fast production ramp Excellent Poor
Lead-times Excellent Poor
JIT delivery Excellent Poor
React to mkt changes Excellent Poor
Min order quantities Low High
Inventory:
Cost of scrap inventory None High
Carrying costs Low High

41. Spartan Advantages Summary
In Design:
Eliminates NRE
Immediate prototypes
No test vectors/ ATPG needed (100% factory tested)
No penalty for design spins with reprogrammability
Broad and verified portfolio of COREs
In Production:
Fast time-to-volume production with “off the shelf” availability
Immediate market penetration
Facilitates JIT delivery
No scrapping inventory
Enables field product updates
FPGA Flexibility at ASIC prices

42. Immediate Production HDL Design Flow
ASIC Replacement FPGAs
ASIC Features
ASIC Pricing
Immediate Production HDL Design Flow
FPGA Flexibility at ASIC Prices!