1. Russell Lindgren Electronics Lead russ.lindgren@lmco.com
HMI00381
HMI Electronics
Russell Lindgren
Electronics Lead

2. Agenda Top Level Requirements Key Drivers Design Considerations
Key Trades
Design Overview
HMI Electronics Box
HEB Packaging
Processor
PCI to Local Bus Bridge/1553 Interface
Mechanism Controllers
Housekeeping Data Acquisition
CCD Camera Interface
Compressor/Spacecraft HSB Interface
Power Converter Subsystem
Oven Controller
Image Stabilization System
Test Plans & Open Issues

3. Top Level Requirements
Provide conditioned power and control for all HMI subsystems
Includes Image Stabilization System and Filter Oven Controller Electronics
Includes Mechanism & Heater Control Electronics
Provide processor for:
Control of all HMI subsystems
Decoding and execution of commands
Acquire and format housekeeping telemetry
Self-contained operation for extended periods
Program modifiable on-orbit
Provide stable jitter free timing reference
Provide compression and formatting of science data from two CCD cameras
Provide dual interface for 55 Mbps of science data
Provide spacecraft 1553 interface:
Commands kbps
Housekeeping telemetry 2.0 kbps
Diagnostic telemetry 10 kbps for short periods upon request

4. Key Drivers Cadence/Data Rate Data Continuity and Completeness Timing
Required cadence is two 4096 x 4096 x 14 bit images every 4 seconds. Requires camera interface link rate of 200 Mbits per second.
Data Continuity and Completeness
HMI requirement is 99.99% of the data 95% of the time. In other words, we need very good data integrity over the 90 second observing periods, and we need the observables for 95% of all observing time.
Timing
The internal reference clock controlling the HMI observing cycle must maintain a stability of one part per million, and must be within 100 mS of the correct absolute time at all times.

5. Design Considerations
Radiation Tolerance
Parts must be latch up free. Parts are chosen to have 100K rad TID. FPGA’s use TMR to avoid single event upsets. Possible SEU issues with Atmel Spacewire ASICs (SMCS332 and SMCSlite) are being worked.
Cross Strapping
Cross strapping (to improve reliability) requires care to insure components are properly cold spared.
Power Sequencing
The BaE Processor card requires proper sequencing of power supply voltages. Also, the Actel FPGA’s require sequencing of power supply voltages to avoid a possible current surge problem.
Parts Selection
Since we are re-using past designs, replacements must be found for some obsolete parts (or old stock must be re-screened).
De-rating
EEE parts must be de-rated in accordance with EEE-INST-0002.

6. Key Trades HMI00195 HMI Processor Trade Study
A trade study was conducted to determine which processor board best met the requirements of HMI. The BAE RAD6000 processor used on a previous program (C) was found to have more than adequate performance and lower risk than other choices. Besides this processor, we looked at a BAE RAD750, BAE RAD6000 (6U), Maxwell SCS750 and General Dynamics RH-CF5208.
HMI00212 HMI Reliability Trade Summary
The proposed instrument was almost entirely single string in nature. A trade study was conducted to investigate ways of enhancing the reliability of HMI. As a result we added redundant tuning mechanisms, a redundant power subsystem, a redundant high speed data interface, a redundant processor, a redundant PCI Bridge/1553 board and a modest amount of electrical cross strapping.
Packaging
Moved connectors to large face of box to improve spacing.
Currently finalizing mechanical design to place I/O connectors on daughter boards to improve routing of traces for high speed signals (Spacewire).

7. Design Overiew
Electronics are included in both the HMI Electronics Box (HEB) and the HMI Optics Package (HOP)
HMI Electronics Box Includes:
RAD6000 Processor Board (2): Specified in 2H00016
PCI to Local Bus Bridge & 1553 Interface Board (2): Specified in 2H00120
Mechanism & Heater Controller Board (4): Specified in 2H00123
Housekeeping Data Acquisition Board: Specified in 2H00121
CCD Camera Interface Board (2): Specified in 2H00124
Data Compressor/High Rate Interface Board (2): Specified in 2H00125
Image Stabilization Subsystem: Specified in 2H00122
ISS Limb Tracker Board
ISS PZT Driver Board
Power Converter Subsystem: Specified in 2H00119
Optics Package Electronics include:
Oven Controller Electronics: Specified in 2H00126
Oven Controller Board (2)
Oven Controller Pre-amp (2)
ISS Electronics
ISS Limb Tracker Pre-amp
CCD Cameras

8. Top Level Block Diagram

9. HMI Electronics Box (HEB)
Most of the HMI electronics are contained in the HEB
Exceptions are Oven Controller Electronics, ISS Pre-amps, and CCD Camera Electronics
Package design is currently being finalized
I/O connectors moved to larger face to increased spacing and placed on daughter boards to minimize trace length for high speed interfaces (Spacewire).
Conservative thermal design
Conductive transfer through base.
Power subsystem components mounted on heat sinks against edges at bottom of box.
Wedge-lock on each card to insure good thermal contact at card edges.
Heat sinks used where thermal analysis indicated necessity.
Operating temperature range specified at 0 to 40 deg C to maximize reliability.
Conservative mechanical design
Stiffeners on printed wiring boards for vibration.
Walls are in thick for radiation shielding (Spacecraft provides 0.040).
Considerable heritage from MDI, TRACE, and other programs (C,D).

10. HEB Packaging
10.0 in H
15.2 in W
11.1 in D

11. HEB Block Diagram

12. Processor Same processor as previous programs (C,D)
2H00016 Specification for the HMI Processor Board
Redundant cold spared processor boards
Mass <900 grams
Power <13.5 W at 20 Mhz
Radiation >100K rad (Si)
SEU <1 upset in 10 years, Latchup immune
SRAM 4 Mbytes
PROM 64 Kbytes
EEPROM 512 Kbytes
EEPROM is powered off during normal operation to reduce radiation damage
Resources
8 External Interrupts
4 Programmable Interrupt/Discretes
Quad High Speed Serial Buses
PCI Bus

13. Processor Block Diagram

14. PCI to Local Bus Bridge
Two redundant cards are cold spared (along with its associated processor).
Specified in 2H00120
Either card can communicate with all other cards.
Resides on processor PCI bus
Provides interface between the Processor card and other parts of the HMI electronics.
Mechanism & Heater Controllers
Image Stabilization Subsystem
Housekeeping Data Acquisition
Power Converter Subsystem
Oven Controller
Provides On Board Clock
System tick to Processor
Shutter Sync
Provides 1553B Interface to Spacecraft

15. PCI to Local Bus Bridge

16. Bridge Board Functions and Requirements
On-Board Clock (OBC)
48 bit real time clock readable by the processor; 32 bits of seconds and 16 bits of sub-seconds.
Must maintain absolute accuracy of .1 sec. May be maintained by adjustments from the processor at a maximum of once per 24 hours.
Must latch time with signals from external events.
Serial Interfaces
Processor must control/configure oven controller and image stabilization system. Must maintain ohmic isolation (isolated grounds).
Mechanism/heater controller must be controlled and status read back to the processor.
Low bandwidth requirements.
Power System Interface
Processor must control relays and LEDs.
Processor readback of relay status required.
Keep the circuitry in the Power System as simple as possible.

17. Bridge Board Functions and Requirements
Housekeeping telemetry interface
Provides an interface for the processor to read analog telemetry points throughout the system.
Must be able to read at a 2.5 Khz rate (ISS requirement).
1553 interface
Must provide a 1553 interface between the spacecraft and the processor.
Interrupts/Time ticks
Must output a 512 hz interrupt to the processor.
Must be synchronized with the On Board Clock.

18. Bridge Board Design OBC Clock is an adder
LSB of clock is 2-16 seconds ( µs).
To maintain .1 sec accuracy over 24 hours requires adjustments of 1 part in 2-23.
To keep count output continuous (no missing counts) need to clock at a µs rate requiring 1 extra bit in increment value for 24 bits total.

19. Bridge Board Design & Status
Serial interfaces
Re-using designs from previous programs (C,D)
100 khz serial clock
16 bit command
8 bit status (mechanism/heater controller only)
Using opto-isolators for ISS and oven controller for return isolation
Housekeeping telemetry interface
Re-used design from previous program (D)
1553 interface
Circuit copied from a previous program (A). Uses same AMBI interface chip.
All functionality is contained in one FPGA
RTL has been written and simulated and meets current requirements
Design has been synthesized and placed and routed to get preliminary numbers on utilization and timing
Preliminary design is complete
Plan to have detailed review after PDR
Open issues include the oscillator to be used for the OBC (stability requirements)

20. Mechanism Controllers
Four cards of two types
Specified in 2H00123.
Provide Mechanism & Operational Heater Interfaces via serial interface to Bridge card.
Each Mechanism Controller card can communicate with either Bridge card.
Redundant mechanisms interface to different controller cards.
15 Mechanisms
Shutters (2)
Cal/Focus Wheels (2)
Polarization Selectors (3)
Tuning Motors (4)
Aperature Door Motors (2)
Alignment Leg Motors (2)
Operational Heaters
Two per board (for a maximum of 8 total)

21. Mechanisms Controllers Block Diagram
Card 1
Card 2
Card 3
Card 4
Tuning Motor 2
Polarization Selector 2
Calibration/Focus Wheel 1
Shutter 2
Heaters 2 & 6
Tuning Motor 1
Polarization Selector 1
Calibration/Focus Wheel 2
Shutter 1
Heaters 1 & 5
Tuning Motor 4
Heaters 4 & 8
Tuning Motor 3
Polarization Selector 3
Alignment Leg 1
Aperture Door 1
Heaters 3 & 7
Alignment Leg 2
Aperture Door 2
Serial Bus A
Serial Bus B
Power +3.3/+5/+15/+28
HMI Electronics Box

22. HMI Mechanisms Controller 1 & 2
Clock
Oscillator
Opto-
Isolators
15V Motor
Phase A
Phase B
Phase C
Drive
MOSFETs
MOSFET
Switch
Encoder
Power
Tuning
Waveplate
Polarization
Selector
Shutter
Enc A
Enc B
Enc C
Switch A
Switch B
Op Heater
IRED
Data
Enable
Status
FPGA
Serial
Control
Bus 1
Bus 2
28V Htr
54LVDS31/32
54ACS14
Alignment
Leg
Board ID
Shutter Openout
54LVDS31
To/From
Other
Boards

23. HMI Mechanisms Controller 3 & 4
Opto-
Isolators
15V Motor
Phase A
Phase B
Phase C
Drive
MOSFETs
MOSFET
Switch
Encoder
Power
Tuning
Waveplate
Door
Motor
Polarization
Selector
Enc A
Enc B
Enc C
Op Heater
28V Htr
54ACS14
Isolator
FPGA
Cal/Focus
Wheel
Open
Close
Clock
Oscillator
Data
Enable
Status
Serial
Control
Bus 1
Bus 2
54LVDS31/32
Board ID
To/From
Other
Boards

24. Housekeeping Data Acquisition
Single card similar to that used in previous program (D)
Specified in 2H00121
Controlled by PCI Local Bus Bridge
Either Bridge card can control Housekeeping Data Acquisition (cold spare)
The Housekeeping Data Acquisition electronics are contained on a single printed wiring board within the HMI Electronics Box. This board contains a 12 bit analog to digital converter, signal conditioning amplifiers, and analog multiplexers for selection of various input sources.
Status
Currently reviewing HMI requirements with goal of using existing design from a previous program (D).
Will need re-layout of board.

25. Housekeeping Data Acquisition

26. CCD Camera Interface Two boards located in the HMI Electronics Box
Specified in 2H00124
The HEB to CEB interface electronics are contained on two identical printed wiring boards within the HEB, one for each camera. Each board provides an interface for commands and housekeeping data between the HMI processor boards and a single CEB, and an interface for science data between a single CEB and either of two Data Compression/High Rate Interface boards.
Commands and status data are passed between either Processor card and the CCD Camera Interface via a High Speed Serial (HSS) Bus in Programmed I/O mode (DMA is not used). HSS words are used either to configure the SMCSlite, or are passed as Spacewire (IEEE 1355) packets by the SMCSlite to the CEB. Status and/or housekeeping packets from the CEB are passed to either Processor A or B after conversion to HSS protocol by the Control and Interface Logic.
CCD camera data (4K x 4K x 16 bits) is transferred as a single Spacewire packet from the CEB to the SMCSlite, and then to buffer memory on the CCD Interface Card. CCD pixels, which are read from each corner of the CCD and interleaved in the Spacewire packet, are deconvolved by the control and interface logic and stored in the buffer memory. Data in the buffer memory may be read by either of the two Compressor/High Rate Interface Cards.
Status
Currently developing detailed specification.

27. CCD Camera Interface

28. Compressor/Spacecraft HSB Interface
Two boards located in HMI Electronics Box
Specified in 2H00125
The Data Compression and Spacecraft High Rate Interface (DC/HRI) electronics are contained on two identical printed wiring boards within the HMI Electronics Box (HEB). Each board provides an interface for commands and header data from either HMI processor board, an interface from either of two CCD Camera Interface boards, and interfaces for high rate science data to either of two Spacecraft High Rate Interfaces. Either board is capable of performing lossless data compression, formatting into CCSDS packets, and outputting of science data at the full data rate allocated to HMI (55 Mbits/sec).
Commands, status and header data are passed between either Processor card and the Compressor/High Rate Interface card via a High Speed Serial (HSS) Bus in Programmed I/O mode (but DMA may be used for table loads). HSS words are used to configure the Interface Control and Compression Logic, to initialize and control the SMCS, or to load header data into the output Buffer Memory.
Status
Currently developing detailed specification

29. Compressor/Spacecraft HR Interface

30. Power Converter Subsystem
Redundant power converters are located within the HMI Electronics Box
Specified in 2H00119
The HEB power electronics is designed to perform two primary functions: convert 28V from the S/C to secondary voltages used by the instrument and route power to the proper HMI sub-system.
The HEB power electronics is powered by either of four spacecraft (S/C) bus inputs, Bus A, Bus A’, Bus B and Bus B’. The S/C 28V is converted into operating voltages for the HEB, the optics package and the Instrument Stabilization System (ISS).
The HEB power electronics switches 28V primary to the two camera sub-systems and the decontamination heaters. Secondary power is routed via latching relays to the mechanisms controllers, oven controllers, operational heaters as well as the HEB computer. The power electronics secondary voltages consist of +3.3V, +5V, +15V and -15V, +72V, +15V operational heater power and +15V mechanisms power.
Key Design requirements
The HMI Power Electronics shall be a redundant system.
The HMI Power Electronics shall not be damaged by simultaneous application of power from the S/C primary and redundant bus.
The HMI Power Electronics secondary power and return lines shall be isolated from the primary power and return lines by >/= 1 Megohm.
HMI Electronics shall meet EMC, grounding and radiation requirements specified in the SDO Electrical System Specification.

31. Power Converter Subsystem

32. Power Converter Subsystem
Design considerations
Cross-strapping the Power Electronics supplies such that the primary supply could supply power to either the primary or redundant HMI subsystem: The study concluded that implementing cross-strapping without discrete commands from the S/C would cause the design of the Power Electronics to become very complex and would lower the reliability of the system.
Using mechanical relays versus solid state switches to route power to the HMI subsystems:
Mechanical latching relays will allow SP/DT functionality needed for the 3.3V power supply and the decontamination heaters. The board design is much simpler and uses less parts with the mechanical relays. Mechanical relays are unaffected by the radiation environment.
Designing an in-rush current limiter into the power electronics: The rise time of the S/C SSPC will allow the HMI instrument to meet the in-rush current specification without in-rush current limiting.
Status
First draft specification complete.
Parts selection complete.
Preliminary layout complete.

33. Oven Controller
Two redundant Controller boards and two redundant pre-amp boards located in the HMI optics package
Specified in 2H00126
The HMI Oven Controller is an updated version of the MDI Primary Oven Controller. It has two identical redundant controllers, with redundant heater elements, temperature sensors and pre-amplifiers. The oven controller electronics are located in the HMI Optics Package, and interface with the PCI/Local Bus Bridge board and the Power Converter Subsystem in the HMI Electronics Box.
Electronics are thermally coupled to oven to enhance stability.
Operating temperature range: deg C
Temperature accuracy: 0.5 deg C
Temperature stability: deg C per hour
Status
Selection of key parts complete.
Preliminary layout complete.
Design update in progress

34. Oven Controller

35. Image Stabilization System
Two boards (Limb Tracker and PZT Driver) located in the HMI Electronics Box, plus pre-amp and sensor boards located in the Optics Package
Specified in 2H00122
The HMI Image Stabilization System (ISS) is a closed loop system with a tip-tilt mirror to remove jitter measured at a primary image within HMI. This system is based on the MDI ISS limb sensor, mirror and servo loop.
Interfaces to the PCI Local Bus Bridge, the Housekeeping Data Acquisition board, and the Power Subsystem.
Status
Selection of key parts complete.
Preliminary layout complete.
Design update in progress

36. Test Plan & Open Issues Breadboard Brassboard Open Issues
Plan to build limited version of backplane and one PCI Bridge/1553 board to support early start to software development
Brassboard
Plan to build brass board system with at least one of each type of board for design verification
Brass board is then used for flight board testing and software development.
During initial phase of integration, brass board electronics may be shared between flight board testing, software development, and flight system integration.
Open Issues
Need to finalize HEB packaging and board layouts.
SEU testing of Atmel SMCSlite.
Need to resolve issues involving use of SDRAM on CCD Interface board (SEU mitigation).