Presentation is loading. Please wait.

Presentation is loading. Please wait.

Parallel to Serial Module

Published byきみとし とくやす Modified over 6 years ago

Similar presentations

Presentation on theme: "Parallel to Serial Module"— Presentation transcript:

1 Parallel to Serial Module
Xinyu Yi Veerasak Nichayapun

2 Overview Layout Synthesis P2S module simulation

3 Layout Syntheis Synopsis Design compiler ( tcl file)
Target frequency in MHz for optimization #set my_clk_freq_MHz 10 # Delay of input signals (Clock-to-Q, Package etc.) #set my_input_delay_ns 0.1 # Reserved time for output signals (Holdtime etc.) #set my_output_delay_ns 0.1

4 Layout Syntheis Initial Timing Report

5 Layout Syntheis Post CTS Timing Report

6 Layout Syntheis Post-Route Timing Report

7 Layout Syntheis Connectivity Verify
******** Start: VERIFY CONNECTIVITY ********Start Time: Tue Jan 25 14:18: Design Name: P2S_Top_v1Database Units: 2000Design Boundary: (0.0000, ) ( , )Error Limit = 1000; Warning Limit = 50Check all netsVC Elapsed Time: 0:00:00.0Begin Summary Found no problems or warnings.End SummaryEnd Time: Tue Jan :18: ******** End: VERIFY CONNECTIVITY ******** Verification Complete : 0 Viols. 0 Wrngs. (CPU Time: 0:00:00.0 MEM: 0.031M)

8 Layout Syntheis Geometry Verify
******** End: VERIFY CONNECTIVITY ******** Verification Complete : 0 Viols. 0 Wrngs. (CPU Time: 0:00:00.0 MEM: 0.031M)encounter 2> *** Starting Verify Geometry (MEM: 315.2) *** VERIFY GEOMETRY Starting Verification VERIFY GEOMETRY Initializing VERIFY GEOMETRY Deleting Existing Violations VERIFY GEOMETRY Creating Sub-Areas bin size: VERIFY GEOMETRY SubArea : 1 of 1 VERIFY GEOMETRY Cells : 0 Viols. VERIFY GEOMETRY SameNet : 0 Viols. VERIFY GEOMETRY Wiring : 0 Viols. VERIFY GEOMETRY Antenna : 0 Viols. VERIFY GEOMETRY Sub-Area : 1 complete 0 Viols. 0 Wrngs.VG: elapsed time: 0.00Begin Summary ... Cells : 0 SameNet : 0 Wiring : 0 Antenna : 0 Short : 0 Overlap : 0 End Summary Verification Complete : 0 Viols. 0 Wrngs. **********End: VERIFY GEOMETRY********** *** verify geometry (CPU: 0:00:00.2 MEM: 4.5M)

9 Layout Syntheis Synthesized layout

10 P2S Module Simulation Three files of FSM, Shift Register and top modules are simulated in Modelsim

11 P2S Module Simulation Technical Problem

12 The End

Download ppt "Parallel to Serial Module"

Similar presentations

Z. Stamenković 1, M. Giles 2, and F. Russi 2 1 IHP GmbH, Frankfurt (Oder), GERMANY 2 Synopsys Inc., Mountain View, CA, USA 13th IEEE European Test Symposium,

Z. Stamenković 1, M. Giles 2, and F. Russi 2 1 IHP GmbH, Frankfurt (Oder), GERMANY 2 Synopsys Inc., Mountain View, CA, USA 13th IEEE European Test Symposium,
TOPIC : SYNTHESIS DESIGN FLOW Module 4.3 Verilog Synthesis.

TOPIC : SYNTHESIS DESIGN FLOW Module 4.3 Verilog Synthesis.
How to get a Circuit in verilog converted to hspice, connected to the micron package models, and simulating in hspice and hsimplus.

How to get a Circuit in verilog converted to hspice, connected to the micron package models, and simulating in hspice and hsimplus.
Electrical and Computer Engineering MIDI Note Number Display UGA Presentation and Demo ECE 353 Lab B.

Electrical and Computer Engineering MIDI Note Number Display UGA Presentation and Demo ECE 353 Lab B.
Logic Synthesis – 3 Optimization Ahmed Hemani Sources: Synopsys Documentation.

Logic Synthesis – 3 Optimization Ahmed Hemani Sources: Synopsys Documentation.
End of Column Circuits Sakari Tiuraniemi - CERN. EOC Architecture 45 9 Ref CLK 40 MHz DLL 32-bit TDC bank address RX 5 TDC bank address RX 5 TDC bank.

End of Column Circuits Sakari Tiuraniemi - CERN. EOC Architecture 45 9 Ref CLK 40 MHz DLL 32-bit TDC bank address RX 5 TDC bank address RX 5 TDC bank.
Shift Register Application Chapter 22 Subject: Digital System Year: 2009.

Shift Register Application Chapter 22 Subject: Digital System Year: 2009.
Integrated Circuits Laboratory Faculty of Engineering Digital Design Flow Using Mentor Graphics Tools Presented by: Sameh Assem Ibrahim 16-October-2003.

Integrated Circuits Laboratory Faculty of Engineering Digital Design Flow Using Mentor Graphics Tools Presented by: Sameh Assem Ibrahim 16-October-2003.
Graduate Computer Architecture I Lecture 15: Intro to Reconfigurable Devices.

Graduate Computer Architecture I Lecture 15: Intro to Reconfigurable Devices.
Nonlinear & Neural Networks LAB. CHAPTER 20 VHDL FOR DIGITAL SYSYEM DESIGN 20.1VHDL Code for a Serial Adder 20.2VHDL Code for a Binary Multiplier 20.3VHDL.

Nonlinear & Neural Networks LAB. CHAPTER 20 VHDL FOR DIGITAL SYSYEM DESIGN 20.1VHDL Code for a Serial Adder 20.2VHDL Code for a Binary Multiplier 20.3VHDL.
The Design Process Outline Goal Reading Design Domain Design Flow

The Design Process Outline Goal Reading Design Domain Design Flow
[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 22 Overall Project Objective : Dynamic Control.

[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 22 Overall Project Objective : Dynamic Control.
Behavioral Design Outline –Design Specification –Behavioral Design –Behavioral Specification –Hardware Description Languages –Behavioral Simulation –Behavioral.

Behavioral Design Outline –Design Specification –Behavioral Design –Behavioral Specification –Hardware Description Languages –Behavioral Simulation –Behavioral.
ECE x26 Laboratory 4 Pavan Gunda. Overview Lab4 is the culmination of all your efforts of both the ECE x25 and ECE x26 labs. Integrates the designs built.

ECE x26 Laboratory 4 Pavan Gunda. Overview Lab4 is the culmination of all your efforts of both the ECE x25 and ECE x26 labs. Integrates the designs built.
2/16/2007EECS150 Lab Lecture #51 Logic Analyzers EECS150 Spring 2007 – Lab Lecture #5 Shah Bawany.

2/16/2007EECS150 Lab Lecture #51 Logic Analyzers EECS150 Spring 2007 – Lab Lecture #5 Shah Bawany.
Vishwani D. Agrawal James J. Danaher Professor

Vishwani D. Agrawal James J. Danaher Professor
Logic Design Outline –Logic Design –Schematic Capture –Logic Simulation –Logic Synthesis –Technology Mapping –Logic Verification Goal –Understand logic.

Logic Design Outline –Logic Design –Schematic Capture –Logic Simulation –Logic Synthesis –Technology Mapping –Logic Verification Goal –Understand logic.
8 Bits Gray Code Converter By: Dawei Kou Flora Wu Linda Htay.

8 Bits Gray Code Converter By: Dawei Kou Flora Wu Linda Htay.
Guest Lecture by Ben Magstadt CprE 281: Digital Logic.

Guest Lecture by Ben Magstadt CprE 281: Digital Logic.
Robust Low Power VLSI R obust L ow P ower VLSI Memory Management Units for Instruction and Data Cache for OR1200 CPU Core Arijit Banerjee ASIC/SOC Class.

Robust Low Power VLSI R obust L ow P ower VLSI Memory Management Units for Instruction and Data Cache for OR1200 CPU Core Arijit Banerjee ASIC/SOC Class.

Similar presentations

Ads by Google