1. ECE 448
Lecture 3
Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic
ECE 448 – FPGA and ASIC Design with VHDL

2. Reading P. Chu, FPGA Prototyping by VHDL Examples
Required
P. Chu, FPGA Prototyping by VHDL Examples
Chapter 3, RT-level combinational circuit
Sections 3.1, 3.2, 3.3, 3.6, 3.7.1,
Recommended
S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design
Chapter 6, Combinational-Circuit Building Blocks
Chapter 5.5, Design of Arithmetic Circuits Using
CAD Tools
ECE 448 – FPGA and ASIC Design with VHDL

3. Types of VHDL Description
(Modeling Styles)
ECE 448 – FPGA and ASIC Design with VHDL

4. Types of VHDL Description
VHDL Descriptions
Testbenches
dataflow
structural
behavioral
Concurrent
statements
Components and
interconnects
Sequential statements
Registers
State machines
Instruction decoders
Subset most suitable for synthesis
ECE 448 – FPGA and ASIC Design with VHDL

5. Register Transfer Level (RTL) Design Description
Today’s Topic
Combinational
Logic
Combinational
Logic …
Registers

6. Synthesizable VHDL VHDL code synthesizable Dataflow VHDL VHDL code
ECE 448 – FPGA and ASIC Design with VHDL

7. Data-Flow VHDL Concurrent Statements
simple concurrent signal assignment ()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)

8. Concurrent signal assignment
<=
target_signal <= expression;
ECE 448 – FPGA and ASIC Design with VHDL

9. Conditional concurrent signal assignment
When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;
ECE 448 – FPGA and ASIC Design with VHDL

10. Selected concurrent signal assignment
With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;
ECE 448 – FPGA and ASIC Design with VHDL

11. Data-Flow VHDL Concurrent Statements
simple concurrent signal assignment ()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)

12. Modeling Wires and Buses
ECE 448 – FPGA and ASIC Design with VHDL

13. Signals a b SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0); a 1
wire b
bus 8
ECE 448 – FPGA and ASIC Design with VHDL

14. Merging wires and buses4 10 b 5
d = a || b || c c
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
d <=
ECE 448 – FPGA and ASIC Design with VHDL

15. Merging wires and buses4 10 b 5
d = a || b || c c
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
d <= a & b & c;
ECE 448 – FPGA and ASIC Design with VHDL

16. Splitting buses a = d .. d b = d .. c = d4 10 d
b = d .. 5
c = d
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
a <=
b <=
c <=
ECE 448 – FPGA and ASIC Design with VHDL

17. Splitting buses a = d9..6 d b = d5..1 c = d04 10 d
b = d5..1 5
c = d0
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
a <= d(9 downto 6);
b <= d(5 downto 1);
c <= d(0);
ECE 448 – FPGA and ASIC Design with VHDL

18. Combinational-Circuit
Building Blocks
ECE 448 – FPGA and ASIC Design with VHDL

19. Fixed Shifters & Rotators
ECE 448 – FPGA and ASIC Design with VHDL

20. Fixed Logical Shift Right in VHDL
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);
A(3)
A(2)
A(1)
A(0) 4 A A
>>1 C L
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required. C 4
‘0’
A(3)
A(2)
A(1)
ECE 448 – FPGA and ASIC Design with VHDL

21. Fixed Logical Shift Right in VHDL
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);
A(3)
A(2)
A(1)
A(0) 4 A A
>>1 C L
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required. C 4
‘0’
A(3)
A(2)
A(1)
C <= '0' & A(3 downto 1);
ECE 448 – FPGA and ASIC Design with VHDL

22. Fixed Arithmetic Shift Right in VHDL
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);
A(3)
A(2)
A(1)
A(0) 4 A A
>>1 C A
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required. C 4
A(3)
A(3)
A(2)
A(1)
ECE 448 – FPGA and ASIC Design with VHDL

23. Fixed Arithmetic Shift Right in VHDL
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);
A(3)
A(2)
A(1)
A(0) 4 A A
>>1 C A
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required. C 4
A(3)
A(3)
A(2)
A(1)
C = A(3) & A(3 downto 1);
ECE 448 – FPGA and ASIC Design with VHDL

24. Fixed Logical Shift Left in VHDL
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);
A(3)
A(2)
A(1)
A(0) 4 A A
<<1 C L
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required. C 4
A(2) A(1) A(0) ‘0’
ECE 448 – FPGA and ASIC Design with VHDL

25. Fixed Logical Shift Left in VHDL
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);
A(3)
A(2)
A(1)
A(0) 4 A A
<<1 C L
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required. C 4
A(2) A(1) A(0) ‘0’
C = A(2 downto 0) & '0';
ECE 448 – FPGA and ASIC Design with VHDL

26. Fixed Rotation Left in VHDL
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);
A(3)
A(2)
A(1)
A(0) 4 A A
<<< 1 C
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required. C 4
A(2)
A(1)
A(0)
A(3)
ECE 448 – FPGA and ASIC Design with VHDL

27. Fixed Rotation Left in VHDL
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);
A(3)
A(2)
A(1)
A(0) 4 A A
<<< 1 C
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required. C 4
A(2)
A(1)
A(0)
A(3)
C = A(2 downto 0) & A(3);
ECE 448 – FPGA and ASIC Design with VHDL

28. Variable Rotators
ECE 448 – FPGA and ASIC Design with VHDL

29. 8-bit Variable Rotator Left3
A <<< B B C 8
To be covered during one of the future classes
ECE 448 – FPGA and ASIC Design with VHDL

30. Gates
ECE 448 – FPGA and ASIC Design with VHDL

31. Basic Gates – AND, OR, NOT × ¼ (a) AND gates x + (b) OR gates1 2 n + ×
(a) AND gates
(b) OR gates
(c) NOT gate
ECE 448 – FPGA and ASIC Design with VHDL

32. Basic Gates – NAND, NOR … …
ECE 448 – FPGA and ASIC Design with VHDL

33. DeMorgan’s Theorem and symbols
for NAND and NOR
ECE 448 – FPGA and ASIC Design with VHDL

34. DeMorgan’s Theorem and other symbols
for NAND, NOR x 1 2 + =
(a)
(b)
ECE 448 – FPGA and ASIC Design with VHDL

35. Basic Gates – XOR (b) Graphical symbol (a) Truth table 1 x f Å =1 x 2 f Å =
(c) Sum-of-products implementation
ECE 448 – FPGA and ASIC Design with VHDL

36. Basic Gates – XNOR x x f = x Å x 1 1 x 1 . f = x Å x = x x x 1 1 12 1 2 1 1 x 1 1 . f = x Å x = x x x 1 2 1 2 1 1 1 2
(a) Truth table
(b) Graphical symbol x 1 x 2 f = x Å x 1 2
(c) Sum-of-products implementation
ECE 448 – FPGA and ASIC Design with VHDL

37. Data-flow VHDL: Exampley s
cin
cout
ECE 448 – FPGA and ASIC Design with VHDL

38. Data-flow VHDL: Example (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fulladd IS
PORT ( x : IN STD_LOGIC ;
y : IN STD_LOGIC ;
cin : IN STD_LOGIC ;
s : OUT STD_LOGIC ;
cout : OUT STD_LOGIC ) ;
END fulladd ;
ECE 448 – FPGA and ASIC Design with VHDL

39. Data-flow VHDL: Example (2)
ARCHITECTURE dataflow OF fulladd IS
BEGIN
s <= x XOR y XOR cin ;
cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;
END dataflow ;
ECE 448 – FPGA and ASIC Design with VHDL

40. Logic Operators Logic operators Logic operators precedence
and or nand nor xor not xnor
only in VHDL-93
and above
Highest
No order precedents
not
and or nand nor xor xnor
Lowest
ECE 448 – FPGA and ASIC Design with VHDL

41. No Implied Precedence Wanted: y = ab + cd Incorrect
y <= a and b or c and d ;
equivalent to
y <= ((a and b) or c) and d ;
y = (ab + c)d
Correct
y <= (a and b) or (c and d) ;
No order precedents
ECE 448 – FPGA and ASIC Design with VHDL

42. Multiplexers
ECE 448 – FPGA and ASIC Design with VHDL

43. 2-to-1 Multiplexer VHDL: s f s w w f w 1 1 1 (a) Graphical symbol1 s f w 1 w 1
(a) Graphical symbol
(b) Truth table
VHDL:
ECE 448 – FPGA and ASIC Design with VHDL

44. VHDL: f <= w1 WHEN s = '1' ELSE w0 ;
2-to-1 Multiplexer f s w 1 s f w 1 w 1
(a) Graphical symbol
(b) Truth table
VHDL: f <= w1 WHEN s = '1' ELSE w0 ; or
f <= w0 WHEN s = '0' ELSE w1 ;
ECE 448 – FPGA and ASIC Design with VHDL

45. Cascade of two multiplexers3 w 1 y 2 w 1 1 s2 s1
VHDL:
ECE 448 – FPGA and ASIC Design with VHDL

46. Cascade of two multiplexers3 w 1 y 2 w 1 1 s2 s1
VHDL:
y <= w1 WHEN s1 = '1' ELSE
w2 WHEN s2 = '1' ELSE
w3 ;
ECE 448 – FPGA and ASIC Design with VHDL

47. Operators Relational operators
Logic and relational operators precedence
= /= < <= > >=
Highest
not
= /= < <= > >=
and or nand nor xor xnor
No order precedents
Lowest
ECE 448 – FPGA and ASIC Design with VHDL

48. Priority of logic and relational operators
compare a = bc
Incorrect
… when a = b and c else …
equivalent to
… when (a = b) and c else …
Correct
… when a = (b and c) else …
No order precedents
ECE 448 – FPGA and ASIC Design with VHDL

49. 4-to-1 Multiplexer s (a) Graphic symbol (b) Truth table f s 1 w 00 0100 01 2 3 10 11 s w 1 f s 2 3
ECE 448 – FPGA and ASIC Design with VHDL

50. 4-to-1 Multiplexer s WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01",
(a) Graphic symbol
(b) Truth table f s 1 w 00 01 2 3 10 11 s w 1 f s 2 3
WITH s SELECT
f <= w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS ;
ECE 448 – FPGA and ASIC Design with VHDL

51. Decoders
ECE 448 – FPGA and ASIC Design with VHDL

52. 2-to-4 Decoder w y (b) Graphical symbol (a) Truth table w y 1 3 w y En2 y 1 3 2 1 y 1 1 y En 1 1 1 1 1 1 1 x x
ECE 448 – FPGA and ASIC Design with VHDL

53. 2-to-4 Decoder w y (b) Graphical symbol (a) Truth table w y 1 3 w y 11 y 3 w x En 2 2 y y 1 y En
ECE 448 – FPGA and ASIC Design with VHDL

54. 2-to-4 Decoder w y Enw <= En & w ; WITH Enw SELECT
(b) Graphical symbol
(a) Truth table w y w 1 3 w y 1 y 3 w x En 2 2 y y 1 y En
Enw <= En & w ;
WITH Enw SELECT
y <= "0001" WHEN "100",
"0010" WHEN "101",
"0100" WHEN "110",
"1000" WHEN "111",
"0000" WHEN OTHERS ;
ECE 448 – FPGA and ASIC Design with VHDL

55. VHDL code for a 2-to-4 Decoder entity
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END dec2to4 ;
ARCHITECTURE dataflow OF dec2to4 IS
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= "0001" WHEN "100",
"0010" WHEN "101",
"0100" WHEN "110",
"1000" WHEN "111",
"0000" WHEN OTHERS ;
END dataflow ;
ECE 448 – FPGA and ASIC Design with VHDL

56. Encoders
ECE 448 – FPGA and ASIC Design with VHDL

57. Priority Encoder y w w w w w y y z 1 1 - 1 - - 1 - - - w y w y w z w 3y y w w 1 y 1 w 2 z w 3 w w w w y y z 3 2 1 1 1 1 - 1 - - 1 - - -
ECE 448 – FPGA and ASIC Design with VHDL

58. Priority Encoder y w d 1 w y z - w y w y w z w 2 3 1 1 2 3y y w w 1 y 1 w 2 z w 3 d 1 w y z - 2 3
ECE 448 – FPGA and ASIC Design with VHDL

59. Priority Encoder y w y <= "11" WHEN w(3) = '1' ELSEy y w w 1 y 1 w
y <= "11" WHEN w(3) = '1' ELSE
"10" WHEN w(2) = '1' ELSE
"01" WHEN w(1) = '1' ELSE
"00" ;
z <= '0' WHEN w = "0000" ELSE '1' ; 2 z w 3 d 1 w y z - 2 3
ECE 448 – FPGA and ASIC Design with VHDL

60. VHDL code for a Priority Encoder entity
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY priority IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z : OUT STD_LOGIC ) ;
END priority ;
ARCHITECTURE dataflow OF priority IS
BEGIN
y <= "11" WHEN w(3) = '1' ELSE
"10" WHEN w(2) = '1' ELSE
"01" WHEN w(1) = '1' ELSE
"00" ;
z <= '0' WHEN w = "0000" ELSE '1' ;
END dataflow ;
ECE 448 – FPGA and ASIC Design with VHDL

61. Adders
ECE 448 – FPGA and ASIC Design with VHDL

62. Adder mod 216 16 16 X Y S 16

63. VHDL code for an Adder mod 216
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.numeric_std.all ;
ENTITY adder16 IS
PORT ( X : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
END adder16 ;
ARCHITECTURE dataflow OF adder16 IS
BEGIN
S <= std_logic_vector(unsigned(X) + unsigned(Y));
END dataflow ;

64. Signed and Unsigned Types
Behave exactly like
STD_LOGIC_VECTOR
plus, they determine whether a given vector
should be treated as a signed or unsigned number.
Require
USE ieee.numeric_std.all;

65. 16-bit Unsigned Adder 16 16 X Y +
Cout
Cin S 16

66. Addition of Unsigned Numbers (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.numeric_std.all ;
ENTITY adder16 IS
PORT ( Cin : IN STD_LOGIC ;
X : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;
Cout : OUT STD_LOGIC ) ;
END adder16 ;

67. Addition of Unsigned Numbers (3)
ARCHITECTURE dataflow OF adder16 IS
signal USum: unsigned(16 DOWNTO 0) ;
signal UCin: unsigned(0 downto 0);
BEGIN
UCin(0) <= Cin;
USum <= unsigned('0' & X) + unsigned(Y) + UCin;
S <= std_logic_vector(Sum(15 downto 0));
Cout <= Sum(16) ;
END dataflow ;

68. Multipliers
ECE 448 – FPGA and ASIC Design with VHDL

69. Unsigned vs. Signed Multiplication
1111 15
1111 -1 x x x x
225 1

70. 8x8-bit Unsigned Multipliera b * c U 16

71. 8x8-bit Signed Multipliera b * c S 16

72. 8x8-bit Unsigned and Signed Multipliercu cs 16 16

73. Multiplication of signed and unsigned numbers
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all ;
entity multiply is
port(
a : in STD_LOGIC_VECTOR(7 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
cu : out STD_LOGIC_VECTOR(15 downto 0);
cs : out STD_LOGIC_VECTOR(15 downto 0) );
end multiply;
architecture dataflow of multiply is
begin
-- signed multiplication
cs <= STD_LOGIC_VECTOR(SIGNED(a)*SIGNED(b));
-- unsigned multiplication
cu <= STD_LOGIC_VECTOR(UNSIGNED(a)*UNSIGNED(b));
end dataflow;

74. Buffers
ECE 448 – FPGA and ASIC Design with VHDL

75. Tri-state Buffer (a) A tri-state buffer (b) Equivalent circuitx f e
= 0
(a) A tri-state buffer x f e x f e
= 1 x f 1 1
(b) Equivalent circuit 1 1
(c) Truth table
ECE 448 – FPGA and ASIC Design with VHDL

76. Tri-state Buffer (a) A tri-state buffer (b) Equivalent circuitx f e
= 0
(a) A tri-state buffer x f e x f e
= 1 x f Z 1 Z 1
(b) Equivalent circuit 1 1 1
(c) Truth table
ECE 448 – FPGA and ASIC Design with VHDL

77. Four types of Tri-state Buffers
ECE 448 – FPGA and ASIC Design with VHDL

78. Four types of Tri-state Buffers
f <= x WHEN (e = '1') ELSE 'Z';
f <= not x WHEN (e = '1') ELSE 'Z';
f <= x WHEN (e = '0') ELSE 'Z';
f <= not x WHEN (e = '0') ELSE 'Z';
ECE 448 – FPGA and ASIC Design with VHDL

79. Tri-state Buffer entity (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tri_state IS
PORT ( e: IN STD_LOGIC;
x: IN STD_LOGIC;
f: OUT STD_LOGIC );
END tri_state;
ECE 448 – FPGA and ASIC Design with VHDL

80. Tri-state Buffer entity (2)
ARCHITECTURE dataflow OF tri_state IS
BEGIN
f <= x WHEN (e = ‘1’) ELSE ‘Z’;
END dataflow;
ECE 448 – FPGA and ASIC Design with VHDL

81. ROM
ECE 448 – FPGA and ASIC Design with VHDL

82. ROM 8x16 example (1) 8x16 ROM Addr Dout C 3 16
ECE 448 – FPGA and ASIC Design with VHDL

83. ROM 8x16 example (2) LIBRARY ieee; USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY rom IS
PORT (
Addr : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) );
END rom;

84. ROM 8x16 example (3) ARCHITECTURE dataflow OF rom IS
SIGNAL temp: INTEGER RANGE 0 TO 7;
TYPE vector_array IS ARRAY (0 to 7) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
CONSTANT memory : vector_array :=
( X”800A",
X"D459",
X"A870",
X"7853",
X"650D",
X"642F",
X"F742",
X"F548");
BEGIN
temp <= to_integer(unsigned(Addr));
Dout <= memory(temp);
END dataflow;

85. ROM 8x16 example (4) ARCHITECTURE dataflow OF rom IS
TYPE vector_array IS ARRAY (0 to 7) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
CONSTANT memory : vector_array :=
( X"800A",
X"D459",
X"A870",
X"7853",
X"650D",
X"642F",
X"F742",
X"F548");
BEGIN
Dout <= memory(to_integer(unsigned(Addr)));
END dataflow;

86. Describing Combinational Logic Using Dataflow Design Style
ECE 448 – FPGA and ASIC Design with VHDL

87. MLU Example
ECE 448 – FPGA and ASIC Design with VHDL

88. MLU Block Diagram A MUX_4_1 NEG_A Y NEG_Y B L1 L0 NEG_B MUX_0 A1 Y11 A1 A
MUX_4_1
IN0 Y1
MUX_1 1
NEG_A
IN1
MUX_2 Y
IN2
OUTPUT
IN3
SEL0
SEL1
NEG_Y 1 B1 B L1 L0
MUX_3
NEG_B

89. MLU: Entity Declaration
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mlu IS
PORT(
NEG_A : IN STD_LOGIC;
NEG_B : IN STD_LOGIC;
NEG_Y : IN STD_LOGIC;
A : IN STD_LOGIC;
B : IN STD_LOGIC;
L1 : IN STD_LOGIC;
L0 : IN STD_LOGIC;
Y : OUT STD_LOGIC );
END mlu;
ECE 448 – FPGA and ASIC Design with VHDL

90. MLU: Architecture Declarative Section
ARCHITECTURE mlu_dataflow OF mlu IS
SIGNAL A1 : STD_LOGIC;
SIGNAL B1 : STD_LOGIC;
SIGNAL Y1 : STD_LOGIC;
SIGNAL MUX_0 : STD_LOGIC;
SIGNAL MUX_1 : STD_LOGIC;
SIGNAL MUX_2 : STD_LOGIC;
SIGNAL MUX_3 : STD_LOGIC;
SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0);
ECE 448 – FPGA and ASIC Design with VHDL

91. MLU - Architecture Body
BEGIN
A1<= NOT A WHEN (NEG_A='1') ELSE A;
B1<= NOT B WHEN (NEG_B='1') ELSE B;
Y <= NOT Y1 WHEN (NEG_Y='1') ELSE
Y1;
MUX_0 <= A1 AND B1;
MUX_1 <= A1 OR B1;
MUX_2 <= A1 XOR B1;
MUX_3 <= A1 XNOR B1;
L <= L1 & L0;
with (L) select
Y1 <= MUX_0 WHEN "00",
MUX_1 WHEN "01",
MUX_2 WHEN "10",
MUX_3 WHEN OTHERS;
END mlu_dataflow;
ECE 448 – FPGA and ASIC Design with VHDL

92. Logic Implied Most Often by Conditional and Selected
Concurrent Signal
Assignments
ECE 448 – FPGA and ASIC Design with VHDL

93. Data-Flow VHDL Concurrent Statements
simple concurrent signal assignment ()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)

94. Conditional concurrent signal assignment
When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;
ECE 448 – FPGA and ASIC Design with VHDL

95. Most often implied structure
When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;
Value N
Value N-1
Condition N-1
Condition 2
Condition 1
Value 2
Value 1
Target Signal … 1 .… 1 1
ECE 448 – FPGA and ASIC Design with VHDL

96. Data-Flow VHDL Concurrent Statements
simple concurrent signal assignment ()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)

97. Selected concurrent signal assignment
With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;
ECE 448 – FPGA and ASIC Design with VHDL

98. Selected concurrent signal assignment
choice_expression
Discrete type or 1-D array
With finite possible values
choices_k
A value of the data type used for choice_expression
Choices must be
Mutually exclusive
All inclusive
OTHERS can be used as a last choice
target_signal and expressions(1..N) must have the same type
ECE 448 – FPGA and ASIC Design with VHDL

99. Most Often Implied Structure
With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;
expression1
choices_1
expression2
choices_2
target_signal
expressionN
choices_N
choice expression
ECE 448 – FPGA and ASIC Design with VHDL

100. Allowed formats of choices_k
WHEN value
WHEN value_1 | value_2 | .... | value N
WHEN OTHERS
ECE 448 – FPGA and ASIC Design with VHDL

101. Allowed formats of choices_k - example
WITH sel SELECT
y <= a WHEN "000",
c WHEN "001" | "111",
d WHEN OTHERS;
ECE 448 – FPGA and ASIC Design with VHDL

102. when-else vs. with-select-when (1)
"when-else" should be used when:
1) there is only one condition (and thus, only one else), as in the 2-to-1 MUX
2) conditions are independent of each other (e.g., they test values of different signals)
3) conditions reflect priority (as in priority encoder); one with the highest priority need to be tested first.
ECE 448 – FPGA and ASIC Design with VHDL

103. when-else vs. with-select-when (2)
"with-select-when" should be used when there is
1) more than one condition
2) conditions are closely related to each other (e.g., represent different ranges of values of the same signal)
3) all conditions have the same priority (as in the 4-to-1 MUX).
ECE 448 – FPGA and ASIC Design with VHDL