1. Data bus
CPU
General Purpose
microprocessor
RAM
ROM
I/O Port
Timer
Serial Com Port
Address bus
General Purpose Microprocessor System
CPU RAM ROM
I/O Timer Serial COM
Port
Microcontroller

2. 8051 Block diagram INT0’ INT1’ Timer1 Timer1 Timer0 T1 Serial port
Interrupt
control
Other
registers
128 Bytes
RAM
ROM 4K
Timer0 T0
CPU
Oscillator
Bus Control
I/O ports
ALE
EA’
P P P P3
RST
TXD’
RXD’
PSEN’

3. 40 19
VCC 32
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
A15
A14
A13
A12
A11
A10 A9 A8
XTL1
XTL2
PSEN’
ALE
EA’
RST
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
12 MHZ 18 39 8
8051
RD’
WR’ T1 T0
INT1’
INT0’
TXD
RXD 17 1 28 10 21
VSS 20

4. 8051 on-chip data memory Byte address Bit address FF
F F7 F6 F5 F4 F3 F2 F1 F0 B
E0 E7 E6 E5 E4 E3 E2 E1 E0 ACC
D0 D7 D6 D5 D4 D3 D D0 PSW
B BC BB BA B9 B8 IP
B B7 B6 B5 B4 B3 B2 B1 B0 P3
A8 AF AC AB AA A9 A8 IE
A0 A7 A6 A5 A4 A3 A2 A1 A0 P2
not bit addressable SBUF
F 9E 9D 9C 9B 9A SCON P1
8D not bit addressable TH1
8C not bit addressable TH0
8B not bit addressable TL1
8A not bit addressable TL0
not bit addressable TMOD
F 8E 8D 8C 8B 8A TCON
not bit addressable PCON
not bit addressable DPH
not bit addressable DPL
not bit addressable SP P0
Byte
address
Bit address 7F
General
Purpose
RAM 30
2F 7F 7E 7D 7C 7B 7A 2E
2D 6F 6E 6D 6C 6B 6A 2C
2B 5F 5E 5D 5C 5B 5A .
F 0E 0D 0C 0B 0A
Bit
Addressable
locations 1F 18 17 10 0F 08 07 00
Bank3
Bank2
Bank1
Default register bank for R0-R7
RAM
Special Function Registers