Microcomputer Systems 1

Microcomputer Systems 1
Digital Systems: Hardware Organization and Design 9/19/2018 Microcomputer Systems 1 Introduction to Visual DSP++ Tools Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design
9/19/2018 Goals Introduction to Visual DSP++ and Tools Specific to Blackfin Information on how to analyze applications and fine tune them. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Outline The VisualDSP++ Tools Creating a Project Plotting Performance improvement using chip features Cache L1 Memory Voltage Regulator 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Blackfin CROSSCORE Product Line
Digital Systems: Hardware Organization and Design 9/19/2018 Blackfin CROSSCORE Product Line VisualDSP++ development suite Performance-tuned C/C++ compiler Source language debugger RTOS kernel (VDK) Device drivers and system services Ethernet and USB 2.0 libraries Tuned DSP libraries Visual linker Code wizards Flash programmer Multicore code generation and debugging Plotting and other advanced code generation and debugging tools Automation API EZ-KIT Lite and Daughter cards ADSP-BF533 ADSP-BF535 ADSP-BF537 ADSP-BF561 A-V EZ-Extender Audio EZ-Extender USB-LAN EZ-Extender FPGA EZ-Extender JTAG Emulators USB 2.0 USB 1.1 PCI Background Telemetry 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Additional Information
Digital Systems: Hardware Organization and Design 9/19/2018 Additional Information ADSP-BF533 EZ-KIT Lite Manual Tools manuals provided in the On-line help Analog Devices web site: Support: For tools questions: For processor questions: Licensing and Registration questions: Or click the “Ask A Question” button 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

DSP Project Development Stages
Digital Systems: Hardware Organization and Design 9/19/2018 DSP Project Development Stages Simulation Evaluation Emulation 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Simulation Development Cycle begins in simulation environment VisualDSP++ with simulation target enables: Building Debugging 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Evaluation EZ-KIT Lite evaluation system in the lab can be used to: Determine Processor Capabilities that best fit target application EZ-KIT Lite Board connected to the PC Development System via USB Port or JTAG interface This connection can be used for Evaluation as well as Emulation purposes (see next slide). Code download via USB Port is significantly slower than JTAG interface used for emulation. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Emulation Actual hardware (can be EZ-KIT Lite board) is connected via JTAG (Joint Test Action Group) emulator We have only 1 JTAG obtained from our winning entry to UML-ADI competition Emulator enables application software to be downloaded and debugged from within VisualDSP++ Emulation Software performs the communications that enables measurement of DSP performance and how current implementation affects it. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Development Tools VisualDSP++ version 4.5 (from Analog Devices) – version 5.0 will be installed soon. Vendors other than Analog Dev.: MULTI from Green Hills Software Open Source GCC tool chain and Clinux 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 VisualDSP++ Project Development and Debugging is integrated (IDDE). C/C++ Native Compiler Graphical Plotting Tools Statistical Profiling Cache Visualization Pipeline Viewer VisualDSP++ Kernel (VDK) 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

ADSP-BF533 EZ-KIT Lite Evaluation System Board
Digital Systems: Hardware Organization and Design 9/19/2018 ADSP-BF533 EZ-KIT Lite Evaluation System Board 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Evaluation Board EZ-KIT LITE
Digital Systems: Hardware Organization and Design 9/19/2018 Evaluation Board EZ-KIT LITE Analog Devices ADSP-BF533 processor Performance up to 600 MHz 160-pin mini-BGA package The Ball Grid Array (BGA) is descended from the pin grid array (PGA), which is a package with one face covered (or partly covered) with pins in a grid pattern. 27 MHz CLKIN oscillator 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Evaluation Board EZ-KIT LITE Synchronous dynamic random access memory (SDRAM) MT48LC32M MB (32M x 16 bits) Flash memories 2 MB (512K x 16 x 2chips) Analog audio interface AD1836 – Analog Devices 96 kHz 24-bit audio codec 4 input RCA phone jacks (2 channels) 6 output RCA phone jacks (3 channels) 2 MB (512K x 16 bits x 2chips) FLASH memory 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Evaluation Board EZ-KIT LITE Analog video interface ADV7183 video decoder w/ 3 input RCA phone jacks ADV7171 video encoder w/ 3 output RCA phone jacks Universal asynchronous receiver/transmitter (UART) ADM3202 RS-232 line driver/receiver DB9 male connector LEDs 10 LEDs: 1 power (green), 1 board reset (red), 1 USB (red), 6 general purpose (amber), and 1 USB monitor (amber) Push buttons 5 push buttons with debounce logic: 1 reset, 4 programmable flags 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Interfaces Expansion interface PPI, SPI, EBIU, Timers2-0, UART, programmable flags, SPORT0, SPORT1 Other features JTAG ICE 14-pin header USB-based debugger interface SPORT0 connector Evaluation suite of VisualDSP++ 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Evaluation Board (cont.)
Digital Systems: Hardware Organization and Design 9/19/2018 Evaluation Board (cont.) 10 LED’s: Power Board Reset USB Reset USB Monitor 6 general-purpose (programmable) 5 Push buttons 1 reset 4 programmable 3 90-pin connectors providing: Parallel Peripheral Interface (PPI) Synchronous Serial Port Interface (SPI) External Bus Interface Unit (EBIU) Timers 0-2 Universal Asynchronous Receiver-Transmitter (UART) Programmable Flags, High Speed Serial Ports (SPORT0 & 1) 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Development Process on DSP
Digital Systems: Hardware Organization and Design 9/19/2018 Development Process on DSP VisualDSP++ Integrated Development & Debugging Environment Architecture of a Respresentative 32 Bit Processor

9/19/2018 Development Process Linker Description File (.ldf) Executable File (.dxe) Debugger (In-Circuit Emulator, Simulator, or EX-KIT Lite) Compiler & Assembler Linker Source Files (.c & .asm) Object Files (.doj) C Run-Time Header (basiccrt.s) Linker Description File (.ldf) 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Bootable Image Executable File (.dxe) Boot Image (.ldr) Programmable Memory Loader/ Writer Loader / Splitter EPROM Boot Code (.dxe) 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Integrated Development & Debugging Environment of VisualDSP++
Digital Systems: Hardware Organization and Design 9/19/2018 Integrated Development & Debugging Environment of VisualDSP++ 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Code Development Tools
Digital Systems: Hardware Organization and Design 9/19/2018 Code Development Tools C/C++ compiler Run-time library with over 100 math, DSP, and C run-time library routines Assembler Linker Splitter Loader Simulator Emulator (EZ-Kit Lite or custom hardware) 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Connecting to Debugging Session
Digital Systems: Hardware Organization and Design 9/19/2018 Connecting to Debugging Session Start -> All Programs -> … -> VisualDSP++ VisalDSP++ when launches for the first time it does not connect to any session (see next slide) Visual DSP++ can connect to a number of different debugging sessions: 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Connecting to Debugging Session EZ-KIT Lite: Dedicated USB connection between the PC and EZ-KIT Lite. Simulator: Software model of the processor. No external hardware is required. Customized to the selected DSP processor: Pipelines Caches Several order of magnitude slower than actual hardware execution. Cycle-accurate simulation (detailed view of processor operations) Functional simulator (quick simulation at the expense of detail). 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Connecting to Debugging Session Emulator: JTAG emulator ideal for connecting to hardware Maximal performance Maximal flexibility Emulator is required to connect to any non-EZ-KIT Lite hardware. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

VisualDSP++ Startup Screen
Digital Systems: Hardware Organization and Design 9/19/2018 VisualDSP++ Startup Screen 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Using VisualDSP++ VisualDSP++ includes basic Linker Description File (.ldf) for each processor type. For Blackfin Processors the default installation path is: Program Files\Analog Devices\VisualDSP 4.5\Blackfin\ldf The four Tutorial exercises will be covered in more detail in the LAB. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Exercise 1. Building and Running a C Program Architecture of a Respresentative 32 Bit Processor

Goals of this Exercise:
Digital Systems: Hardware Organization and Design 9/19/2018 Goals of this Exercise: Learn to: Start up the VisualDSP++ environment Open and build an existing project Examine windows and dialog boxes Run the program 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Additional Information The source files for this exercise are in the dot_product_c folder. Default installation path: Program Files\Analog Devices\VisualDSP 4.5\Blackfin\Examples\Tutorial\dot_product_c 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 1: Start VisualDSP++ and Open a Project
Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Start VisualDSP++ and Open a Project Click the Windows Start button and select: Programs, Analog Devices, VisualDSP++ 4.5, and VisualDSP++ Environment. When you need to connect to a debug session, click the Connect to Target toolbar button or choose from the available sessions listed under Select Session in the Session menu. To create a debug session, select New Session from the Session menu. This will launch the Session Wizard, which is covered in more detail later. If you have already run VisualDSP++ and the Reload last project at startup option is selected on the Project page under Settings and Preferences, VisualDSP++ opens the last project that you worked on. To close this project, choose Close and then Project from the File menu, and then click No when prompted to save the project. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Start VisualDSP++ and Open a Project From the File menu, choose Open and then Project. VisualDSP++ displays the Open Project dialog box. Copy content of dotprodc folder: Program Files\Analog Devices\VisualDSP4.5\Blackfin\Examples\ Tutorial\dotprodc This path is based on the default installation. To: u:\ece3551\lab1\ In the Look in box, open the folder u:\ece3551\lab1\ 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Start VisualDSP++ and Open a Project Double-click the dotprodc project (.dpj) file. VisualDSP++ loads the project in the Project window, as shown 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Start VisualDSP++ and Open a Project From the Settings menu, choose Preferences to open the Preferences dialog box, as shown 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Start VisualDSP++ and Open a Project On the General page, under General Preferences, ensure that the following options are selected. Run to main after load Load executable after build Click OK to close the Preferences dialog box. The VisualDSP++ main window appears. You are now ready to build the project. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 dot_prod_c Project The dotprodc project comprises two C language source files: dotprod.c and dotprod_main.c, which define the arrays and calculates their dot products. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 2: Building the dotprodc Project
Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Building the dotprodc Project Running the Compiler Linker Description File (.ldf) Executable File (.dxe) Debugger (In-Circuit Emulator, Simulator, or EX-KIT Lite) Compiler & Assembler Linker Source Files (.c & .asm) Object Files (.doj) C Run-Time Header (basiccrt.s) Linker Description File (.ldf) 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Building the dotprodc Project Linking Linker Description File (.ldf) Executable File (.dxe) Debugger (In-Circuit Emulator, Simulator, or EX-KIT Lite) Compiler & Assembler Linker Object Files (.doj) Source Files (.c & .asm) C Run-Time Header (basiccrt.s) Linker Description File (.ldf) 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Building the dotprodc Project From the Project menu, choose Build Project. VisualDSP++ first checks and updates the project dependencies and then Builds the project by using the project source files. Output window displays status messages. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Building the dotprodc Project 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Building the dotprodc Project Upon successful build (compile and link steps) example program can be run. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 3: Configuring the Session to Run the Program
Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Configuring the Session to Run the Program Before running the program: Set up the debug session. View debugger windows and dialog boxes. Note: In Preferences dialog box of the General page: Load executable after build is checked ⇒ automatic loading of dotprodc.dxe on to the target (EZ-LIT Lite). If not connected to a debug target, VisualDSP++ will prompt to connect to one using an existing debug session or creating a new debug session as shown in the next slide: 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Configuring the Session to Run the Program Clicking OK will launch the Session Wizard as shown in the next slide. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Configuring the Session to Run the Program 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Configuring the Session to Run the Program Setting up debug session: On the Select Processor page, select the ADSP-BF533 processor from the Blackfin family. Click Next to continue. On the Select Connection Type page, select Simulator, and click Next to continue. On the Select Platform page, select ADSP-BF5xx Single Processor Simulator. You can either use the default Session name, or give it a more meaningful name of your choosing. Click Next to review your choices, then click Finish. VisualDSP++ closes the Session Wizard dialog box, automatically loads your project’s executable file (dotprodc.dxe), and advances to the main function of your code. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Configuring the Session to Run the Program 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Configuring the Session to Run the Program Look at the information in the open windows. The Output window’s Console page contains messages about the status of the debug session. In this case, VisualDSP++ reports that the dotprodc.dxe load is complete. The Disassembly window displays the assembly code for the executable. Use the scroll bars to move around the Disassembly window. Note that a solid red circle and a yellow arrow appear at the start of the program labeled “main”. The solid red circle (●) indicates that a breakpoint is set on that instruction, and the yellow arrow (➨) indicates that the processor is currently halted at that instruction. When VisualDSP++ loads your C program, it automatically sets several breakpoints. Most of the breakpoints set are used as part of advanced features of VisualDSP++. There are two breakpoints of interest for this tutorial, one at the beginning and one at the end of code execution. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Configuring the Session to Run the Program From the Settings menu, choose Breakpoints to view the breakpoints set in your program. VisualDSP++ displays the Breakpoints dialog box, as shown. The two breakpoints of interest are set at these C program locations: at main + 0x04 at __lib_prog_term 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Step 4: Run dotprodc To run dotprodc.dxe: Click Run button: Select Run from Debug Menu. VisualDSP++ computes the dot products and displays the following results on the Console view of the Output window. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Exercise 2: Modifying a C Program Code to Call an Assembly Routine Architecture of a Respresentative 32 Bit Processor

9/19/2018 Goals of this Exercise Learn to: Modify the C program to call an assembly language routine Create a Linker Description File (.ldf) to link with the assembly routine Rebuild the project. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Additional Information Ensure that the previous project and its files are closed: From File menu, choose Close and then Project dotprodc. Click Yes when prompted to close all open source windows. Important Note: If you have modified your project during the first exercise you will be prompted to save the project. Click No. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 1: Creating a New Project
Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Creating a New Project From the File menu, choose New and then Project to open the Project Wizard: 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Creating a New Project In the Name field, type dot_product.asm Click the browse button to the right of the Directory field to open the Browse For Folder dialog box. Locate the dot_product_asm tutorial folder and click OK. By default this directory is in the following location. Program Files\Analog Devices\VisualDSP 4.5\Blackfin\ Examples\Tutorial\dot_product_asm Click Next to bring up the Output Type page. Verify that the Processor type is ADSP-BF533, the Silicon Revision is Automatic, and the Project output file is Executable file. Click Next to display the Add Startup Code/LDF page. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Creating a New Project Read the displayed text, and scroll down to the bottom of the page. Select the Add an LDF and startup code option. When this project is created: Startup code that initializes and configures the processor will be added to the project, as well as a Linker Description File that defines the target memory map and the placement of program sections within processor memory. The options available to configure the startup code and LDF are beyond the scope of this tutorial. Make sure the Add an LDF and startup code option is selected, and click Finish. The new project is created and is shown in the Project window of the IDDE. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Creating a New Project From the Project menu click the Project Options command to display the Project Options dialog box 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Creating a New Project On the Project page (see previous slide) verify that the values shown in the following table (or image of the previous slide) are entered. Field Value Processor ADSP-BF533 Revision Automatic Type Executable file Name dot_product_asm Settings for Configuration Debug 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Creating a New Project Take a moment to view the various pages in the Project Options dialog box by selecting them from the tree on the left: Project, General, Compile, Assemble, Link, Load, Pre-Build, and Post-Build. On each page, you specify the tool options used to build the project. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Creating a New Project Click the Compile tab to display the General page, shown: 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Creating a New Project Specify these settings in the Code Generation group box: Select the Enable optimization check box to enable optimization. Select the Generate debug information check box, if it is not already selected, to enable debug information for the C source. Click OK to apply changes to the project options and to close the Project Options dialog box. Note: These settings direct the C compiler to optimize code for the ADSP-BF533 processor. Because the optimization takes advantage of DSP architecture and assembly language features, some of the C debug information is not saved. Therefore, debugging is performed through debug information at the assembly language level. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 2: Adding Source Files to dot_product_asm
Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Adding Source Files to dot_product_asm To add the source file to the new project: Click the Add File button , or from the Project menu, choose Add to Project, and then choose File(s). The Add Files dialog box appears. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Adding Source Files to dot_product_asm 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Adding Source Files to dot_product_asm In the Look in box, locate the project folder, dot_product_asm. In the Files of type box, select All Source Files from the drop-down list. Hold down the Ctrl key and click dotprod.c and dotprod_main.c. Then click Add. To display the files that you added in step 4, open the Source Files folder in the Project window. Click the Rebuild All button ( ) to build the project. The C source file opens in an editor window, and execution halts. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 2: Modifying the Project Source Files
Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Modifying the Project Source Files In this procedure we will: Modify dotprod_main.c to call a_dot_asm instead of a_dot_c Save the modified file 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Modifying the Project Source Files To modify dotprod_main.c to call assembly function a_dot_asm do the following: Resize or maximize the editor window for better viewing From the Edit menu, choose Find to open the Find dialog box as shown in the figure. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Modifying the Project Source Files In the Find What box, type “/*”, and then click Mark All. The editor bookmarks all lines containing “/*” and positions the cursor at the first instance of “/*” in the extern int a_dot_c_asm declaration. Select the comment characters “/*” and Use the Ctrl+X key combination to cut the comment characters from the beginning of the a_dot_c_asm declaration. Then move the cursor up one line and use the Ctrl+V key combination to paste the comment characters at the beginning of the a_dot_c declaration. Because syntax coloring is turned on, the code changes color as you cut and paste the comment characters. Repeat this step for the end-of-comment characters “*/” at the end of the a_dot_c_asm declaration. The a_dot_c declaration is now fully commented out, and the a_dot_c_asm declaration is no longer commented. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Modifying the Project Source Files Press F2 to move to the next bookmark. The editor positions the cursor on the “/*” in the function call to a_dot_c_asm, which is currently commented out. Note that the previous line is the function call to the a_dot_c routine. Press Ctrl+X to cut the comment characters from the beginning of the function call to a_dot_c_asm. Then move the cursor up one line and press Ctrl+V to paste the comment characters at the beginning of the call to a_dot_c. Repeat this step for the end-of-comment characters “*/”. The main() function is now calling the a_dot_c_asm routine instead of the a_dot_c function (previously called in Exercise One). Note: The next image displays the changes made in the step 6. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Modifying the Project Source Files 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Modifying the Project Source Files From the File menu, choose Save and then File dotprod_main.c to save the changes to the file. Place the cursor in the editor window. Then, from the File menu, choose Close and then File dotprod_main.c to close the dotprod_main.c file. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 3: Use the Expert Linker to Modify dot_prod_asm.ldf
Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Use the Expert Linker to Modify dot_prod_asm.ldf In this procedure we will: View the Expert Linker representation of the .ldf file that is created. Modify .ldf file to map in the section for the a_dor_c_asm assembly routine. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Use the Expert Linker to Modify dot_prod_asm.ldf To examine and then modify dot_prod_asm.ldf to link the assembly function do the following: Click the Add File button . Select dotprod_func.asm and click Add. Build the project by performing one of these actions: Click the Build Project button From the Project menu, choose Build Project. Notice the error in the Output window. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Use the Expert Linker to Modify dot_prod_asm.ldf Output Window: Linker Error To correct this error the do the following: 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Use the Expert Linker to Modify dot_prod_asm.ldf In the Project window, double-click in the dot_prod_asm.ldf file. The Expert Linker window (see Figure in the next slide) opens with a graphical representation of your file. Resize the window to expand the view and change the view mode. To display the tree view shown in next slide, right-click in the right pane, choose View Mode, and then choose Memory Map Tree. The left pane (Input Sections) contains a list of the input sections that are in your project or are mapped in the .LDF file. A red X is over the icon in front of the section named “my_asm_section” because Expert Linker has determined that the section is not mapped by the .LDF file. The right pane (Memory Map) contains a representation of the memory segments that Expert Linker defined when it created the .LDF file. Expert Linker Window depicts the procedure followed in this step. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Use the Expert Linker to Modify dot_prod_asm.ldf 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Use the Expert Linker to Modify dot_prod_asm.ldf Map my_asm_section into the memory segment named MEM_PROGRAM as follows. In the Input Sections pane, open my_asm_section by clicking on the plus sign in front of it. The input section expands to show that the linker macros: $COMMAND_LINE_OBJECTS and $OBJECTS and the object file dotprod_func.doj have a section that has not been mapped. In the Memory Map pane, expand MEM_L1_CODE and drag the icon in front of $OBJECTS onto the program_ram output section under MEM_L1_CODE. As shown in Figure in the next slide, the red X should no longer appear because the section my_asm_section has been mapped. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Use the Expert Linker to Modify dot_prod_asm.ldf 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Use the Expert Linker to Modify dot_prod_asm.ldf From the Tools menu, choose Expert Linker and Save to save the modified file. Then close the Expert Linker window. If you forget to save the file and then rebuild the project, VisualDSP++ will see that you modified the file and will automatically save it. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 4: Rebuild and Run dot_prod_asm
Digital Systems: Hardware Organization and Design 9/19/2018 Step 4: Rebuild and Run dot_prod_asm Build the project by: Click the Build Project button , or From the Project menu, choose Build Project. At the end of the build, the Output window should display this message in the Build view: “Build completed successfully” VisualDSP++ loads the program Runs to main, and Displays the Output, Disassembly, and editor windows (as seen in the next slide) 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 4: Rebuild and Run dot_prod_asm 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 4: Rebuild and Run dot_prod_asm Click the Run button to run dot_product_asm. The program calculates the three dot products and displays the results in the Console view of the Output window. When the program stops running, the message “Halted” appears in the status bar at the bottom of the VisualDSP++ main window. The results, shown below, are identical to the results obtained in Exercise One. Dot product [0] = Dot product [1] = – Dot product [2] = 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design Plotting Data
9/19/2018 Exercise 3 Plotting Data Architecture of a Respresentative 32 Bit Processor

9/19/2018 Goals of this Exercise Learn to: Load and debug a prebuilt program that applies a simple Finite Impulse Response (FIR) filter to a buffer of data Use VisualDSP++’s plotting engine to view the different data arrays graphically, both before and after running the program. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digression: What is an FIR Filter
Digital Systems: Hardware Organization and Design 9/19/2018 Digression: What is an FIR Filter Digital Filtering, in general, is one of the most powerful tools of Digital Signal Processing. In general any Digital Signal Processing of a Linear Time Invariant (LTI) system can be expressed with a difference equation (more on this latter) 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Linear Constant-Coefficient Difference Equations
Digital Systems: Hardware Organization and Design 9/19/2018 Linear Constant-Coefficient Difference Equations Nth-order linear constant-coefficient difference equation is of the form: Accumulator Example 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Linear Constant-Coefficient Difference Equations (cont.)
Digital Systems: Hardware Organization and Design 9/19/2018 Linear Constant-Coefficient Difference Equations (cont.) x[n] y[n] One-sample delay 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

General Formulation of Difference Equation
Digital Systems: Hardware Organization and Design 9/19/2018 General Formulation of Difference Equation Equation: Along with initial conditions: y[-1], y[-2], …, y[-N] Uniquely specifies the LTI system. General equation must be computed using recursive procedure. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Example Recursive Computation of Difference Equations: y[n] = ay[n-1]+x[n] Initial condition is given by y[-1] = c; Input x[n] = K[n] Solution n≥0: y[0] = ac+K y[1] = y[0]+0 = a(ac+K) = a2c+aK … y[n] = an+1c+anK, n≥0 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Example (cont.) Solution n<0: y[n] = ay[n-1]+x[n] ➲ y[n-1] = a-1(y[n]-x[n]) y[-1] = c y[-2] = a-1(y[-1]-x[-1]) = a-1 (c+0) = a-1c … y[n] = an+1c, n<0 Overall solution y[n] = an+1c+Kanu[n], n 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Z-Transform Interesting specific class of rational functions of the form: Roots of the polynomial P(z) define the zeros, and Roots of the polynomial Q(z) define the poles of the z-transform. Partial fraction expansion method can be used for rational functions. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Difference Equation & Z-Transform
Digital Systems: Hardware Organization and Design 9/19/2018 Difference Equation & Z-Transform By definition variable Z is equal to unit delay. There is direct relationship between difference equation and Z-Transform: 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Property of Z-Transform
19 September 2018 Veton Këpuska

Difference Equation & Z-Transform
Digital Systems: Hardware Organization and Design 9/19/2018 Difference Equation & Z-Transform Last expression is a rational function with numerator and denominator that are polynomials of z-1. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 Filters Any Linear Time Invariant digital filter is expressed by its difference equation. There are two classes of digital filters: Finite Impulse Response (FIR), and Infinite Impulse Response (IIR). 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 FIR Filters The impulse response of an FIR filter has finite duration and corresponds to having no denominator in the rational function H(z): ➨ There is no feedback in the difference Equation. This results in the reduced form difference equation: Impulse sample response (input x[0]=1; x[n]=0 elsewhere for n≠0) of FIR filter is: 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 1: Loading the FIR Program
Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Loading the FIR Program Keep the Disassembly window and Console page (of the Output window) open, but close all other windows. From the File menu, choose Load Program or click The Open a Processor Program dialog box appears. Select the FIR program to load as follows. Open the Analog Devices folder and double-click: VisualDSP 4.5\Blackfin\Examples\Tutorial\fir Double-click the Debug subfolder. Double-click FIR.DXE to load the program. If VisualDSP++ does not open an editor window (shown in Figure in the next slide), right-click in the Disassembly window and select View Source. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Loading the FIR Program 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Loading the FIR Program Look at the source code of the FIR program. You can see two global data arrays: IN OUT You can also see one function, _fir, that operates on these arrays. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 2: Opening a Plot Window
Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Opening a Plot Window From the View menu, choose Debug Windows and Plot. Then choose New to open the Plot Configuration dialog box, shown in the next slide Figure. Here you add the data sets that you want to view in a plot window. In the Plot group box, specify the following values. In the Type box, select Line Plot from the drop-down list. In the Title box, type fir. Enter two data sets to plot by using the values in Table in the slide after next. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Opening a Plot Window 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 2: Table Specifying 2 Data sets: Input & Output
Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Table Specifying 2 Data sets: Input & Output Box Input Data Set Output Data Set Description Name Input Output Data set Memory BLACKFIN Memory Data memory Address IN OUT The address of this data set is that of the Input or Output array. Click Browse to select the value from the list of loaded symbols Count 128 The array is 260 elements long, but you are plotting the first 128 elements Stride 1 The data is contiguous in memory Data short Input & Output are arrays of 16-bit values After entering each data set, click Add to add the data set to the Data sets list on the left of the dialog box. The Plot Configuration dialog box should now look like the one in the Figure presented in the next slide. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Opening a Plot Window Plot Configuration Dialog Box with Input/Output Data Sets 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Opening a Plot Window Click OK to apply the changes and to open a plot window with these data sets. The plot window now displays the two arrays. By default, the simulator initializes memory to zero, so the Output data set appears as one horizontal line, shown in Figure below. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Opening a Plot Window Right-click in the plot window and choose Modify Settings. On the General page, in the Options group box, select Legend and click OK to display the legend box. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 3: Run the FIR Program and View the Data
Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Run the FIR Program and View the Data Press F5 or click the Run button to run to the end of the program. When the program halts, you see the results of the FIR filter in the Output array. The two data sets are visible in the plot window, as shown in Figure below: 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Run the FIR Program and View the Data Additional Features of the Plotting interface allows you to select the region and to zoom in. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Run the FIR Program and View the Data 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Run the FIR Program and View the Data To return to the view before magnification, right-click in the plot window and choose Reset Zoom from the pop-up menu. Individual data points can be viewed as described in the following procedure: Right-click inside the plot window and choose Data Cursor from the pop-up menu. Move to each data point in the current data set by pressing and holding the Left (←) or Right (→) arrow key on the keyboard. To switch data sets, press the Up (↑) or Down (↓) arrow key. The value of the current data point appears in the lower-left corner of the plot window, as shown in Figure in the next slide. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Run the FIR Program and View the Data 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Run the FIR Program and View the Data Right-click in the plot window and choose Data Cursor from the pop-up menu. Next you will look at data sets in the frequency domain. Right-click in the plot window and choose Modify Settings to open the Plot Settings dialog box. Complete these steps: Click the Data Processing tab to display the Data Processing page, shown in next Figure. In the Data Sets box, ensure that Input (the default) is selected. In the Data Process box, choose FFT Magnitude. In the Sample rate (Hz) box, type In the Data Sets box, select Output. In the Data Process box, choose FFT Magnitude Click OK to exit the Plot Settings dialog box. VisualDSP++ performs a Fast Fourier Transform (FFT) on the selected data set before it is plotted. The FFT enables you to view the signal in the frequency domain, as shown in Figure after next. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Run the FIR Program and View the Data Data Processing Page 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Run the FIR Program and View the Data FFT Performed on a Selected Data Set 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 4: Analysis of the Data
Digital Systems: Hardware Organization and Design 9/19/2018 Step 4: Analysis of the Data FIR filter’s response in the frequency domain From the View menu, choose Debug Windows and Plot. Then choose New to open the Plot Configuration dialog box. Set up the Filter Frequency Response plot by completing the Plot and Data Setting group boxes as shown in Figure in the next slide. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 4: Analysis of the Data 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 4: Analysis of the Data Click Add to add the data set to the Data sets box. Click OK to apply the changes and to open the plot window with this data set. Right-click in the plot window and choose Modify Settings to open the Plot Settings dialog box. Click the Data Processing tab to display the Data Processing page. Complete this page as follows. In the Data Sets box, select h. In the Data Process box, choose FFT Magnitude. In the Sample rate (Hz) box, type Click OK to exit the Data Processing page. VisualDSP++ performs a Fast Fourier Transform (FFT) on the selected data set, and enables you to view the filters frequency response plot in the frequency domain, as shown in Figure in the next slide. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 4: Analysis of the Data Filter’s Frequency Response Plot 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 4: Analysis of the Data This plot shows that the low-pass FIR filter cuts off all frequency components above 4,000 Hz. When you apply this low-pass filter to the input signal, the resulting signal has no output above 4,000 Hz. On the importance of filtering more later: Telephony toll-quality signal requires that signal has no frequency components above 4000 Hz to avoid aliasing. The effect of aliasing is depicted as a low frequency noise “reflected” from the components above 4000 Hz. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design Linear Profiling
9/19/2018 Exercise 4 Linear Profiling Architecture of a Respresentative 32 Bit Processor

9/19/2018 Goals of this Exercise Learn to: Load and debug the FIR program from the previous exercise 3 Use linear profiling to evaluate the program’s efficiency and to determine where the application is spending the majority of its execution time in the code 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

VisualDSP++ Profiling
Digital Systems: Hardware Organization and Design 9/19/2018 VisualDSP++ Profiling VisualDSP++ supports two types of profiling: linear and statistical. Linear Profiling: You use linear profiling with a simulator. The count in the Linear Profiling Results window is incremented every time an assembly instruction is executed. Statistical Profiling: You use statistical profiling with a JTAG emulator connected to a processor target. The count in the Statistical Profiling Results window is based on random sampling of the program counter. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 1: Loading the FIR Program Close all open windows except the Disassembly window and the Output window. Keep the Disassembly window and Console page (of the Output window) open, but close all other windows. From the File menu, choose Load Program or click The Open a Processor Program dialog box appears. Select the FIR program to load as follows. Open the Analog Devices folder and double-click: VisualDSP 4.5\Blackfin\Examples\Tutorial\fir Double-click the Debug subfolder. Double-click FIR.DXE to load and run the FIR program. If VisualDSP++ does not open an editor window, right-click in the Disassembly window and select View Source. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 2: Opening the Profiling Window
Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Opening the Profiling Window From the Tools menu, choose Linear Profiling and then choose New Profile. The Linear Profiling Results window opens without any data. Click in the profiling window’s title bar and then drag and drop the window to the top of the VisualDSP++ main window, as shown in Figure in the next slide. You will have a better view of the profile data. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Opening the Profiling Window 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/19/2018 Step 2: Opening the Profiling Window The Linear Profiling Results window is initially empty. Linear profiling is performed when you run the FIR program. After you run the program and collect data, this window displays the results of the profiling session. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 3: Collecting & Examining the Linear Profiling Data
Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Collecting & Examining the Linear Profiling Data Press F5 or click to run to the end of the program. When the program halts, the results of the linear profile appear in the Linear Profiling Results window. Examine the results of your linear profiling session. The Linear Profiling Results window is divided into two three-column panes. The left pane shows the results of the profile data. You can see the percentages of total execution time consumed, by function and by address. Double-clicking a line with a function enables you to display the source file that contains that function. For example, double-click the fir function to display the assembly source file (fir.asm) in the right pane, as shown in Figure in the next slide. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Step 3: Collecting & Examining the Linear Profiling Data
Digital Systems: Hardware Organization and Design 9/19/2018 Step 3: Collecting & Examining the Linear Profiling Data Linear Profiling Results, FIR Program Performance Analysis. Note: your results may be slightly different. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Interpreting Collected Data
Digital Systems: Hardware Organization and Design 9/19/2018 Interpreting Collected Data Histogram A graphical representation of the percentage of time spent in a particular execution unit. This percentage is based on the total time that the program spent running, so longer bars denote more time spent in a particular execution unit. The Linear Profiling Results window always sorts the data with the most time-consuming (expensive) execution units at the top. % The numerical percent of the same data found in the Histogram column. You can view this value as an absolute number of samples by right-clicking in the Linear Profiling Results window and by selecting View Sample Count from the pop-up menu. Execution Unit The program location to which the samples belong. If the instructions are inside a C function or a C++ method, the execution unit is the name of the function or method. For instructions that have no corresponding symbolic names, such as hand-coded assembly or source files compiled without debugging information, this value is an address in the form of PC[xxx], where xxx is the address of the instruction. If the instructions are part of an assembly file, the execution unit is either an assembly function or the assembly file followed by the line number in parentheses. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Interpreting Collected Data
Digital Systems: Hardware Organization and Design 9/19/2018 Interpreting Collected Data In previous Figure, the left pane shows that the fir function consumes over 96% of total execution time. The right (source) pane, shown in next Figure, displays the percentage that each line in the fir function consumes. 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Linear Profile Data for fir.asm
Digital Systems: Hardware Organization and Design 9/19/2018 Linear Profile Data for fir.asm 19 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/19/2018 End of Tutorial Architecture of a Respresentative 32 Bit Processor

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