GR716 Microcontroller for Space Applications

GR716 Microcontroller for Space Applications
Cobham Gaisler AB 16 June Presenters name: Sandi Habinc Bari, Italy Commercial in Confidence (for public view)

Cobham Gaisler AB Founded in 2001 Located in Gothenburg, Sweden
Official name since 10 December 2014 Founded in 2001 Located in Gothenburg, Sweden Fully owned subsidiary of Cobham plc (UK) Management team with 60 years combined experience in the space sector: Sandi Habinc, General Manager Per Danielsson, Senior Advisor Jan Andersson, Director of Engineering 25 employees with expertise within microelectronics and software design Complete design facilities in-house for ASIC and FPGA development 9 M$ turnover 2016

Standards are fantastic!
19 September 2018

Standards are fantastic! Everyone should have his own.
19 September 2018

Standards are fantastic. Everyone should have his own
Standards are fantastic! Everyone should have his own. We are talking about interfaces. 19 September 2018

Standards are fantastic. Everyone should have his own
Standards are fantastic! Everyone should have his own. We are talking about interfaces. One bus to rule them all. 19 September 2018

We CAN do it! 19 September 2018

We CAN do it! J. Howard Miller 19 September 2018

We CAN do it! Yes, we CAN! 19 September 2018

We CAN do it! Yes, we CAN! Barack Obama 19 September 2018

We CAN do it! Yes, we CAN! Let’s make CAN great again!
19 September 2018

We CAN do it! Yes, we CAN! Let’s make CAN great again!
Ronald Reagan 19 September 2018

We CAN do it. Yes, we CAN. Let’s make CAN great again
We CAN do it! Yes, we CAN! Let’s make CAN great again! CAN should be forbidden in space until engineers learn how to use it. 19 September 2018

We CAN do it. Yes, we CAN. Let’s make CAN great again
We CAN do it! Yes, we CAN! Let’s make CAN great again! FPGAs should be forbidden in space until engineers learn how to use it. Sandi Habinc 19 September 2018

First there was Luca Stagnaro.
19 September 2018

First there was Luca Stagnaro. Then there was Gianluca Furano.
19 September 2018

First there was Luca Stagnaro. Then there was Gianluca Furano
First there was Luca Stagnaro. Then there was Gianluca Furano. And then there was Lucy 19 September 2018

First there was Luca Stagnaro. Then there was Gianluca Furano
First there was Luca Stagnaro. Then there was Gianluca Furano. And then there was Lucy - GR716 Microcontroller (a friend of Leon). 19 September 2018

SPARC/LEON Processor Background
An open non-proprietary standard for space – 25 years in space! Availability to the European space market in 1990 8-bit processors, like 80S32 and 8086 16-bit RISC processors, like MIL-STD-1750, MDC281, MA31750 Motorola 68020, 32-bit CISC – Ariane 5 OBC (launcher) Intel 386, 32-bit CISC – Columbus Laboratory OBC (ISS) European Space Agency (ESA) studies RISC Evaluation Study (Saab Space), 1990 RISC Architecture and Technology (Sagem), 1990 Selection criteria for a new architecture Widely supported, Open architecture, License free SPARC was selected SPARC in Space Atmel has shipped more than 8’500 flight parts since 1994 Cobham has shipped more than 1’500 flight parts since 2007 Unique situation with a multitude of silicon sources 25 years of experience, large installed base

LEON Processor History
Evolution of a SPARC solution over time – 20 years in space! LEON1 processor core Developed at the European Space Agency (ESA) by Jiri Gaisler in 1997 SPARC V8 32-bit architecture / five stage pipeline LEON2 processor core Developed at Gaisler Research (S) under ESA funding in 2002 AMBA AHB and APB on-chip bus, Debug Support Unit (DSU) GNU LGPL, freely available source code LEON3 processor core Completely new development at Gaisler Research (S) in 2004 SPARC V8 32-bit architecture / seven stage pipeline GNU GPL / commercial dual licensing LEON4 processor core Completely new development at Aeroflex Gaisler (S) in 2010 Wider internal bus structures, L2 cache, higher performance LEON5 processor core Completely new development at Cobham Gaisler (S) in 2017 Specification phase started in 2016

LEON Processor History
Evolution of a SPARC solution over time – 20 years in space! LEON1 processor core Developed at the European Space Agency (ESA) by Jiri Gaisler in 1997 SPARC V8 32-bit architecture / five stage pipeline LEON2 processor core Developed at Gaisler Research (S) under ESA funding in 2002 AMBA AHB and APB on-chip bus, Debug Support Unit (DSU) GNU LGPL, freely available source code LEON3 processor core Completely new development at Gaisler Research (S) in 2004 SPARC V8 32-bit architecture / seven stage pipeline GNU GPL / commercial dual licensing LEON4 processor core Completely new development at Aeroflex Gaisler (S) in 2010 Wider internal bus structures, L2 cache, higher performance LEON5 processor core Completely new development at Cobham Gaisler (S) in 2017 Specification phase started in 2016 LEON64 processor core Future development at Cobham Gaisler (S) in … the future SPARC V9 – 64-bit architecture

GR712RC Dual-Core LEON3FT Processor
Dual-core processor with flight heritage TowerJazz 180 nm CMOS technology TID 300 krad(Si); SEL: LET > 118 MeV/cm2/mg; 1.8V core, 3.3V I/O voltage Power consumption (typical): 15 mW / MHz (dual core, MMU, FPU) Dual Core LEON3FT Fault-tolerant processor (SMP) 32 KiB cache with 4 parity bits per word CQFP240, 0.5 mm pitch, 32x32 mm, hermetically sealed

GR740 Quad-Core LEON4FT Processor
European Microprocessor development Quad-core LEON4FT rad-tolerant SoC device 4x LEON4FT with dedicated FPU and MMU 128 KiB L1 caches connected to 128-bit bus 2 MiB L2 cache, 256-bit cache line, 4-ways 64-bit SDRAM memory I/F (+32 checkbits) 8-port SpaceWire router with +4 internal ports 32-bit 33 MHz PCI interface 2x 10/100/1000 Mbit Ethernet Debug links: Ethernet, JTAG, SpaceWire MIL-STD-1553B 2x CAN 2.0B controller interface 2 x UART SPI master/slave, GPIO, Timers & Watchdog LGA625 / CGA625 package ST 65nm bulk CMOS process ESA’s Next Generation Microprocessor (NGMP) activity Worst-case frequency of 250 MHz in production tests Power consumption (including I/O) at 40°C: 4x CPU: 1.85 W (1700 DMIPS) Tested prototype parts and evaluation boards available Qualification funded: QML-V and QML-Q at end of 2018

GR732 Triple-Core Digital Signal Processor
European DSP development 2x Recore Systems Xentium Fixed-Point VLIW DSP 32-bit DSP cores, with parallel functional units 16 kB Instruction (Code) Cache Memory 32 kB Tightly-Coupled Memory 64 kB Memory Tile Network-on-a-Chip (NoC) interconnect 1x Cobham Gaisler LEON3 Fault-Tolerant SPARC V8 Single general-purpose 32-bit / 16-bit processor core 16 kB Data and Memory Cache Memories Memory Management Unit High-Performance IEEE-754 Floating Point Unit Debug Support Unit and Trace Buffers Memory and Error Detection & Correction Support Input/Output Interfaces 4x SpaceWire with RMAP target, up to 200 Mbps Parallel Chip-to-Chip Communication Interface 16 GPIO, PWM, UART, SPI, I2C 2x CAN 2.0B, up to 1 Mbps Low-speed ADC, 13-bit, 833ksps Low-speed current DAC, 12-bit High-speed ADC, 15-bit, 100 Msps 352 pin QFP, 48 mm x 48 mm ESA funded development Prototypes in Q4 2017 Qualification in 2018

GR716 Single-Core LEON3FT Microcontroller
European Microcontroller development LEON3FT - Fault-tolerant SPARC V8 32-bit processor, 50 MHz 16-bit instruction set support to improve code density Floating Point Unit Memory protection units Non-intrusive advanced on-chip debug support unit External EDAC memory: 8-bit PROM/SRAM, SPI, I2C SpaceWire interface with time distribution support, 100 Mbps MIL-STD-1553B interface 2x CAN 2.0B controller interface PacketWire with CRC acceleration support Programmable PWM interface SPI with SPI-for-Space protocols UARTs, I2C, GPIO, Timers with Watchdog Interrupt controller, Status registers, JTAG debug, etc. ADC 200Ksps, 4 differential or 8 single ended DAC 3Msps, 4 channels Mixed General purpose inputs and outputs Power-on-Reset and Brown-out-detection Temperature sensor, Integrated PLL On-chip regulator for 3.3V single supply 132 pin QFP, 24 mm x 24 mm ESA funded development of prototypes in Q1 2018 Qualification funding available in 2019 from SNSB

GR716 – LEON3FT Microcontroller
Introduction Description The GR716 features a fault-tolerant LEON3 SPARC V8 processor, communication interfaces and on-chip ADC, DAC, Power-on-Reset, Oscillator, Brown-out detection, LVDS transceivers, regulators to support for single 3.3V supply, ideally suited for space and other high-rel applications Applications • propulsion system control • sensor bus control • robotics applications control • simple motor control • mechanism control • power control • particle detector instrumentation • radiation environment monitoring • thermal control • antenna pointing control • remote terminal unit control • simple instrument control Specifications • System frequency up-to 50 MHz • SpaceWire links up-to 100 Mbps • CQFP132 hermetically sealed ceramic package • Total Ionizing Dose (TID) up to 100 krad (Si, functional) • Single-Event Latch-Up (SEL) to LETTH > 118 MeV-cm2mg • Single-Event Upset (SEU) below bit error rate • Support for single 3.3V supply 26

Key features – processor and memory Processor core Fault-tolerant SPARC V8 processor with 31 register windows and support 16-bit instruction operation (REX) Double precision IEEE-754 floating point unit Memory protection units with 8 zones and individual access control of peripherals Advanced on-chip debug support unit with trace buffers and statistics Deterministic software execution and non-intrusive debugging Fast context switching (PWRPSR, AWP, register partitioning, interrupt mapping, SVT, MVT) Interrupt zero jitter delay Memory support 192KiB EDAC protected tightly coupled memory with single cycle access from processor and ATOMIC bit operations Embedded ROM with bootloader for initializing and remote access Dedicated SPI Memory interface with boot ROM capability I2C memory interface with boot ROM capability 8-bit SRAM/ROM I/F with support up to 16MiB ROM and 256MiB SRAM Scrubber with programmable scrub rate for all embedded memories and external PROM/SRAM and SPI memories Redundant boot memory (PROM/SRAM/SPI/I2C/NVRAM) Application software container for checking software integrity using CRC Boot from internal SRAM, external PROM/FLASH/SRAM/SPI/I2C memory REX AWP Fault-tolerant SPARC V8 processor External SRAM Internal FLASH NVM (Package option) External FLASH On-Chip Instruction memory (Rad Hard Internal SRAM) On-Chip Data (Rad Hard Internal SRAM) External I2C External SPI (NVM) Internal SRAM NVM (Package option) External I2C (Red) External SPI (NVM) (Red) Support of many variety of memory types 27

Memory support On-chip SRAM w/ Dual Port, EADC and Scrubbing, Radiation Tolerant 192 KiB Instruction and Data – User defined mix of instruction vs data External SPI Interface EDAC, Scrubbing and dual redundancy External SRAM Memory interface PROM/SRAM/MRAM support Up to 6 independent chip selects External I2C Memory Dual redundancy and CRC-16 protection System In Package Memory interface (future option) External SRAM Internal FLASH NVM (Package option) External FLASH On-Chip Instruction memory (Rad Hard Internal SRAM) On-Chip Data (Rad Hard Internal SRAM) External I2C External SPI (NVM) Internal SRAM NVM (Package option) External I2C (Red) External SPI (NVM) (Red) Support of many variety of memory types 28

Boot options Remote boot (no software or external memory required) UART SpaceWire RMAP SPI / SPI4SPACE I2C But no support for CAN! (Why is there no RMAP defined for CAN?) Internal Boot PROM supported boot (configures the I/0s): External PROM/SRAM External SPI Memory Embedded NVRAM/PROM/SRAM in package (future option) External I2C PROM Direct boot (bypass internal boot prom) 29

Key features – system support System On-chip voltage regulators for single supply support. Capability to sense core voltage for trimming of the embedded voltage regulator for low power applications. Power-on-reset, Brownout detection and Dual Watchdog for safe operation. External reset signal generation for companion chips. Crystal oscillator support One PLL for System and SpaceWire clock generation. In-application programming of system clock and peripheral clocks. System and SpaceWire clocks switches glitch free. Low power mode and individual clock gating of functions/peripherals Temperature and core voltage sensor External voltage reference for precision measurement 4x programmable DMA controllers. DMA transfers can be triggered on event such as interrupts, timer overflow for,bit/register value change Timer units with seven 32-bit timers including watchdog Multiple bus structures for non-intrusive debug, DMA transfers and memory scrubbers. Atomic access support for all registers Statistics unit for profiling of the system Support for NVRAM (SRAM and/or PROM) embedded in package Support for software boot and execution from embedded ram for future package options 30

Key features - peripherals Peripherals SpaceWire with support for RMAP and Time Distribution Protocol Redundant MIL-STD-1553B BRM (BC/RT/BM) interface Two CAN 2.0B bus controllers – four busses Six UART ports, with 16-byte FIFO Two SPI master/slave serial ports One SPI controller. Hardware support for protocol 0, 1 and 2 in SPI for Space slave Two I2C master/slave serial port PacketWire interface PWM with up-to 16 channels Up to 64 General input and outputs (GPIO) with external interrupt capability, pulse generation and sampling. 4x single ended Digital to Analog Converters (DAC), 12-bit at 3MS/s 4x differential or 8x single ended Analog to Digital Converters (ADC) 11-bit at 200KS/s, with programmable pre-amplifier and support for oversampling External ADC and DAC support up to 16-bit at 1MS/s 31

Key features – real time Real Time features and enhancements Fast context switching (PWRPSR, AWP, Register partitioning, interrupt mapping, SVT, MVT) Interrupt zero jitter delay Advanced on-chip debug support unit with trace buffers and statistic unit Deterministic software execution and non-intrusive debugging Interrupt Service Routine (ISR) is a user function Normal C function Nesting and chaining with libbcc Fast interrupt SPARC assembly CPU register limitations Measurements on LEON3 GR716: Unit: #cycles. (cycles have to be added) for long instructions (FPU, DIV, etc) at IRQ. Improved system responsiveness Improved determinism Typical Worst IRQ to ISR ISR EXIT BCC 1.0 ISR 196 139 322 - BCC 2.0 ISR 100 73 200 146 Fast interrupt 11 6 32

Key features - constant interrupt delay Support for applications requiring constant interrupt delay Programmable delay in processor from interrupt assertion -> start of trap handler. Ongoing instruction will finish but ‘jump’ instruction to trap handler will be held for time set by user. (worst case is floating point instructions) Timestamp of interrupts and local counter in processor Access to counter in processor and single cycle access to local instruction memory guarantees no extra delay or jitter Possible to set fix delay for trap handler to increase system determinism Make use of all 31 available register windows not to get window overflow or overflow Fixed delay of X cycles Fixed delay guaranteed by trap handler Source Interrupt Ctrl IRQ LEON3FT Trap Handler ISR Timestamp ACK Hardware Software(BCC) Application Asynchronous Constant Delay Application depended 33

Key features – tightly coupled local memory The microcontroller has local instruction and data on-chip RAM connected to the LEON3FT processor Local RAM features: 128KiB Instruction memory single cycle access 64KiB Data memory protected by EDAC Scrubber support Dual port access enable seamless uploading of new program into instruction memory DMA traffic direct into data memory with disturbing program execution or data fetch scrubber access and EDAC correction affect program execution or data fetch Support atomic bit-filed operations OR, AND, XOR, Set & Clear Instructions can be executed from data memory and data can be stored in instruction memory Local instruction and data memory is located close to LEON3FT processor for single cycle access

Key features - Direct Memory Access Controller – one for all peripherals System DMA overview 4 individual DMA cores (each core has multiple channels) Multiple AHB interface and direct access to APB Peripheral Programmable DMA transfers through stand-alone DMA controller Responds to Interrupts, Polling register, Loop support Responds to combination of interrupt and register polling Programmable DMA user scenarios Offload processor Autonomous transfers from/to ADC/DAC without CPU intervention Autonomous transfers between: UART to UART, SPI to SPI or I2C to I2C Transfer data, update register synchronous to event e.g. PWM output levels I2C DMA AMBA AHB AMBA APB AHB APB Bridge DMA Controller LEON3FT SPARC V8 Mul Trace 64kB D-ram FPU SPI GPIO PWM Ext ADCDAC Onchip ADCDAC Config & Status Scrub & ahbstat AMBA 128kB I-ram REX Main AMBA AHB IrqCtrl & Timers UART Descriptors list for fast access via DMA bus peripherals access via dedicated interface 35

Key features – 16-bit support designed with ABI compatibility ABI (Application Binary Interface) Standard for how software communicates at lowest level Which registers to place function arguments in Linker relocations, stack layout, function epilogue and prologue LEON-REX 16-bit instruction set was designed to follow the SPARC ABI Dynamic switching between 32 and 16-bit operating mode Link software compiled for LEON-REX with software compiled for standard SPARC Use the same linker for 32-bit and for 16-bit ISA Allows you to gradually introduce LEON-REX Comparing code size between SPARC 32-bit and LEON-REX 32-bit Boot software: 33% reduction in code size Newlib: 20% reduction in code size RTEMS: 15% reduction in code size Fully working implementation of a LEON-REX compiler based on LLVM. LLVM compiler used to validate hardware implementation. LLVM generates larger object files than GCC for SPARC. Room for improvements both for SPARC and LEON-REX backend.

Key features – inputs/outputs I/O Configurable I/O selection matrix with mixed signals, internal pull-up/pull-down resistors LVDS transceivers for SpaceWire or SPI4Space Clock and reset for companion chips e.g. GPIO-e xpander, external RAM etc. Dedicated SPI boot ROM for configuration External Brown Out detection signal LVDS Interface for SpaceWire or SPI4SPACE Support SPI Memory Sense and reset SpaceWire clock and PLL status DSU enable, break supply Oscillator Watchdog active SPI Memory Error LVDS LDO XO & BO PLL CLKGATE LEON3 192K RAM DSU IRQ & TIMERS LSTAT DUART SPIM SPW SPI4S MCTRL SPI UART ADCDAC I2C GPIO 1553B SPW CAN PW SPI4S ADCDAC GPREG 37 Configurable I/O selection Select Digitial or Analog I/0

Key features – radiation tolerance and package Radiation Tolerance Technology: 180 nm process, UMC Taiwan Library: DARE180+lLibrary version 5.5, IMEC TID: up to 100 krad(Si) SEL: > 118 MeV-cm2/mg SEU: Proven tolerance with hardened flip-flops and Error corrections on all on-chip and external memories Package 132 pin CQFP, mm pitch, 24mm x 24mm, hermetically sealed with flat pins and insulating lead-frame for custom trim and form Support for build-in NVRAM for future package option. 38

Key features – single supply Supply Single 3.3V±0.3V supply or separate Core Voltage 1.8V±0.18V, I/O voltage 3.3V±0.3V Brown-Out detection for all supplies (sense in package) On-chip Linear regulators with possibility to trim core voltage for lowest power consumption Core Voltage sense via internal ADC. (precision measurement) Possible to trim via digital logic Possible to measure via internal ADC Connect external Core supply (1.8V) to ground via decoupling capacitors for single 3.3V supply 39

Key features – a minimum of external parts Minimum application requirements: 3.3V supply frequency resonator in the range of 5MHz to 25MHz de-coupling capacitor reference resistor Minimum application enables system clock and reset remote access to GR716 via SpaceWire, SPI, UART and I2C access to all functions 40 Cobham Proprietary Use or disclosure of this information is subject to the restrictions on the title page of this document

Analogue architecture I2C Memory Controller Mil-1553B BC/RT/MT SpaceWire Links RMAP CAN 2.0 PacketWire SPI GPIO DMA Controller PWM Scrub & ahbstat LEON3FT SPARC V8 Mul Trace 64kB D-ram FPU AMBA 128kB I-ram REX Prot Embeeded Boot ROM IrqCtrl & Timers UART SPI4S BandGap Ref LVDS BO POR XO PLL LDO (PLL) Mixed GPIO MUX ADC LDO (Core) Control & Status LVDS MUX Clock Logic Onchip ADCDAC Digital Mux Logic Digital GPIO WDT Logic Reset Logic Debug SPIM Temp Sensor Core Voltage Sence Internal Ref gen VREF 5.11Kohm C_1v8V 3.3V Supply 1.8V Supply C_RST C_PLL Ext Reset Ext Clock Ext Xtal 4Mhz – 25Mhz DAC Integrated LDO Integrated BO and POR Integrated XO Integrated PLL Option to integrate and support to integrate upto 6 in package memories External Voltage Clock and Reset generation External Voltage Ref FLASH ROM LVDS Tranceivers SRAM Temp sensor Core sense Dual 11b ADC 8 single or 4 differential Pre-amplifier Four 12b DAC 41

Digital architecture – bus structure Multiple APB busses for master access control and non-intrusive debug and DMA AHBSTAT Onchip ADC & DAC Bridge Debug Unit (DSU) I2C DMA AMBA AHB AMBA APB 0 Memory Controller Serial Link RS232 SPI 1553 A/B Mil-1553B BC/RT/MT SpaceWire Links RMAP CAN 2.0 LVDS / LVTTL CAN N/R DMA Controller I/O Port LEON3FT SPARC V8 Mul Trace 64kB D-ram FPU PacketWire GPIO External ADC & DAC PWM UART Config & Status Scrub & ahbstat AMBA 128kB I-ram REX Main AMBA AHB Prot Embeeded Boot ROM IrqCtrl & Timers Onchip ADCDAC SPI2AHB I2C2AHB SPI4S Scrubber Bus Debug Control Reset / Clock Reset / Watchdog Clock DBG AMBA BO POR BO LDO NVRAM AMBA APB 1 Ext ADC SpacWire TDP AUART AMBA APB 3 SPI Memory Ext PROM/SRAM Memory AMBA APB 4 Status and Control Scrubber do not affect master bus Access control build-in to APB controller 42

Digital architecture – plenty is not enough Support for AWP and fast context switch FPU and 32bit MUL 192KiB EDAC Prot Mem Single cycle instruction execution Determenistic execution and interrupt latency RMAP Support TDP Support Debug Link Inst/AHB trace Non-Intrusive HW support for Protocol level 0,1 and 2 Debug Unit (DSU) I2C AMBA AHB AMBA APB SRAM AHB APB Bridge Memory Controller PROM Serial Link RS232 SPI 1553 A/B Mil-1553B BC/RT/MT SpaceWire Links RMAP CAN 2.0 LVDS / LVTTL CAN N/R DMA Controller I/O Port LEON3FT SPARC V8 Mul Trace 64kB D-ram FPU PacketWire GPIO External ADC & DAC PWM Ext ADCDAC Onchip ADCDAC Onchip ADC & DAC Config & Status Scrub & ahbstat AMBA 128kB I-ram REX Prot Embeeded Boot ROM IrqCtrl & Timers UART SPI2AHB I2C2AHB SPI4S Scrubber Bus Debug Control Reset / Clock Reset / Watchdog Clock ATOMIC Op (OR, AND, XOR, Set&Clr) EDAC support Scrubber Dedicated interface available DMA with direct access to periherals Memory Protection Access Restriction Support for future RAM in package Scrubber Direct Access Statistics for profiling System Error detection 43

Digital architecture – CAN details GR716 have 2 separate GRCAN controllers with internal DMA engines (same as used in AT7913E (SPW-RTC), COLE, GR740, GR732 (SSDP)) Based upon CAN core from OpenCores Direct access to memory and timestamping of packets GR716 supports multiple CAN transceivers via IO multiplexer Remote access or Boot over CAN supports requires application software to be placed in external SPI RAM/PROM LEON3FT SPARC V8 CAN Controller A CAN BUS SPI PROM CAN Controller B On-Chip Data RAM 44

Development Platform – software development environment BCC2 Development Environment GCC or LLVM 4.0.0 GRMON2 debugger tool Runs on PC (Windows or Linux) Tightly coupled to LEON debug unit and trace buffers Communicates with ASIC/FPGA via several debug links: UART, JTAG, SpW, etc. 45

Development Platform – evaluation boards FPGA prototype board Platform for early access Full access to all peripherals & functions (some reduction on I/O interfaces) Mezzanine boards for adding interfaces Standard PC debug communications Compatible with BCC2 environment ASIC evaluation board Modular design build for reuse in system GR-board compatible mezzanine pinstack uC Board Full access to all peripherals Standalone: power via mezzanine or AC-adapter Interface Board(s) Special function or interface board (memories, interface phys etc.) Motherboard(s) Application specific boards Connect ‘uC Board’ and ‘Interface Boards’ Power supply Possible to connect front panel 46

Thank you for your attention!
19 September 2018

CAN in Space Workshop [tentative name]
Gothenburg, 12th-14th June 2019

GR716 Microcontroller for Space Applications

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