1. ASP-H Clocks
John DeHart Applied Research Laboratory Computer Science and Engineering Department

2. VirtexII Pro Clock Resources
16 Clock Pads
16 Clock Inputs (IBUFGs)
represent the clock inputs in VHDL
8 Differential Clock Inputs (IBUFGDSs)
represent the differential clock input pairs in VHDL
Use of any of these replaces/consumes two IBUFGs and two clock pads!!
16 BUFGMUXs which are either:
BUFG : global clock buffer
BUFGCE : global clock buffer with enable
can turn clocks off when their modules are not in use
2 versions, one for rising edge clocked circuits one for falling edge clocked circuits.
BUFGMUX : global clock multiplexer
have capability to switch between two clocks
12 Digital Clock Managers (DCMs)
deskew and generate clocks as a function of input clock
Backbone
24 horizontal and vertical long lines routing resources
Skew minimized by PAR if USELOWSKEWLINES constraint is attached to the net.
for use if we need more than the 16 clocks provided.
Need to understand the actual characteristics of these

3. VirtexII Pro Clock Resources

4. Clock Multiplexer Locations

5. Clock Multiplexor Rules
BUFG#P and BUFG#S cannot be used in same quadrant
They share quadrant routing resources
So, for example, if BUFG3P is used in Quadrant 1 , BUFG3S cannot be used in Quadrant 1.
Hence, if there is a clock that is used in all four quadrants its “facing” clock cannot be used at all!
we need to watch out for this with out 125 MHz core clock
Rule 2:
Adjacent clock multiplexors share two inputs

6. DCMs

7. DCMs (continued) Outputs:
CLK0, CLK90, CLK180, CLK270: phase shifts of CLKIN
CLK2x, CLK2x180: double rate, double rate phase shift
CLKDV: CLKIN/CLKDV_DIVIDE
paramterized clock division
CLKFX: CLKIN*CLKFX_MULTIPLY/CLKFX_DIVIDE
parameterized function

8. ASP-H Clock Issues What clocks do we need and at what frequencies?
In what quadrants are each of the clocks needed?
Be aware of LVDS clocks when counting pins/bufs
they consume 2 pins and/or clock buffers

9. ASP-H Clock Needs FPGA Core Logic Clock: 125 MHz Interface to CRM’s
1 IBUFG (1 clock pin)
1 BUFG
Interface to CRM’s
???
RocketIO
2 IBUFGDS
4 clock pins
4 IBUFGs consumed
4 BUFGs
2 DCMs
Running Totals:
IBUFG/pins:?/?
BUFG: ?/?
DCM:?

10. ASP-H Clock Needs (continued)
PPC:
Suggested design #0 (PCI Bus design):
CPU: 300 MHz
PLB: 100 MHz
OPB: 100 MHz
DCR: 100 MHz
Other Cores (hopefully they all run at least as fast as PLB/OPB buses): 100 MHz
This can be accomplished with:
REFCLK = 100 MHz
1 DCM
3 BUFGs
CPU Clock (DCM0:CLKFX(CLKFX_MULTIPLY=3, CLKFX_DIVIDE=1))
PLB/OPB/DCR/Cores (DCM0: CLK0)
DDR Clock (DCM0: CLK2X)
1 IBUFG
REFCLK = 100MHz
2 OBUFs
LVDS clock signals from DDR SDRAM core to DDR
Running Totals:
IBUFG/pins:??/??
BUFG: ??
DCM:??

11. RocketIO Clock Needs One of these for Top and one for Bottom.
REFCLK = 1/20 (Data Rate);
for 2.5 Gb/s, REFCLK=125 MHz
Xilinx Rocket IO Transceiver User Guide v2.3, Page 47