1. SAT-Based Logic Optimization and Resynthesis
Alan Mishchenko
Robert Brayton
UC Berkeley

2. Outline Motivation for resynthesis Brief history of don’t-cares
Our contribution
Algorithm overview
Algorithm components
Experimental results
Conclusion

3. Motivation Several stages of design flow benefit from resynthesis
post-mapping area optimization
critical path synthesis
placement-aware resynthesis
high-effort technology-independent synthesis
Requirements for a resynthesis engine
substantial logic restructuring
capability to be tuned for solving a variety of optimization tasks
reasonable runtime for large designs
Our solution
SAT-based resynthesis with don’t-cares using resubstitution

4. Brief History of Don’t-Cares
Previous century work ( )
Complete rather than compatible don’t-cares (2002)
SAT-based don’t-care optimization (2005)
Interpolation-based optimization with don’t-cares without explicitly computing don’t-cares (this talk)

5. Big Picture Previous approaches Observations K-LUT network
Improved K-LUT network
resynthesis 
Previous approaches
Compute a subset of don’t-cares using SOPs or BDDs
Use Espresso to minimize the nodes while performing resubstitution
Observations
No need for don’t-care computation, BDDs, and Espresso
Simulation generates candidates, SAT proves them
Interpolation derives resubstitution functions
(Unexpectedly, SPFDs came into the picture)

6. Contributions Improved SAT-based resubstitution Improved windowing
evaluates multiple candidates simulation and SAT
utilizes internal don’t cares without computing them
derives resubstitution functions via interpolation using SAT solver
Improved windowing
structural analysis avoids non-reconvergent paths, generating windows with more internal flexibilities
new rugged window computation works for large networks containing nodes with multiple fanouts
Experiments on industrial benchmarks

7. Background Summary Assuming the audience is familiar with:
Networks and nodes
Cuts and cones
Don’t-cares and resubstitution
Optimization with don’t-cares
Interpolation
Structural choices

8. Proposed Algorithm Consider all or some nodes in some order Windowing
Divisor selection
Candidate set filtering using simulation
Checking resubstitution using SAT
Computing resubstitution function
Updating the network

9. Windowing Definition A window includes Improvements to windowing
A window for a node is the node’s context, in which an operation is performed
A window includes
k levels of the TFI
m levels of the TFO
all re-convergent paths between window PIs and window POs
Improvements to windowing
Replace deep traversal from window PIs to window POs, by a shallow traversal from node to window POs, to avoid traversing multiple fanout nodes
Exclude those window POs that do not have reconvergent paths to window PIs
Window POs
Window PIs
k = 3
m = 3
Pivot node

10. Divisor Selection
Divisor is a candidate fanin of the pivot node after resubstitution
Divisor computation:
Partition window PIs into
(a) those in the TFI node of the pivot
(b) the remaining window PIs
Add nodes between the pivot and window PIs of type (a), excluding the node and the node’s MFFC
Add nodes in the window if their structural support has no window PIs of type (b)
Do not collect divisors whose level exceed a limit
Do not collect more than a given number of divisors
Window POs
m = 3
Pivot node
k = 3
type (b)
type (b)
type (a)
Window PIs

11. Resubstitution
Resubstitution of F(x) with care set C(x) and candidate functions {gi(x)} exists iff every pair of care minterms, x1 and x2, distinguished by F(x), is also distinguished by gi(x) for some i
That is, if information of F(x) does not exceed that of {gi(x)}
Example:
Given F = (a  b)(b  c), C = 1
Two candidate sets:
{y1= a’b, y2 = ab’c},
{y3= a  b, y4 = bc}
Set {y1, y2} is feasible
Set {y3, y4} is infeasible
Counter-example: x1 = 100, x2 = 101
abc F y1 y2 y3 y4
000
001
010 1
011
100
101
110
111

12. Resubstitution Candidate Filtering
Use simulation to test if resubstitution exists with a given set of candidate functions, {gi(x)}
Simulate random vectors through the window
Remove patterns x that are not in the care set: C(x) = 0
For every pair of patterns, x1 and x2, such that F(x1)  F(x1) = 1, check if gi(x1)  gi(x2) = 0 for all i
If this is true, candidate functions {gi(x)} cannot resubstitute F(x)

13. Checking Resubstitution using SAT
If the SAT problem is unsatisfiable, resubstitution of function F(x) with care set C(x) and candidate functions {g1(x), g2(x), g3(x)} exists.

14. Computing Dependency Function
Definition of the interpolant:
Consider A(x, y) and B(y, z), such that A(x, y)  B(y, z) = 0, where x and z appear only in the clauses of A and of B, respectively, and y are variables common to A and B.
An interpolant of function A(x, y) w.r.t. function B(y, z) is a Boolean function, I(y), depending only on the common variables y, such that A(x, y)  I(y) and I(y)  (y, z).
Problem:
Find function h(g), such that h(g(x)) can replace f(x) on care set C(x), that is, C(x)  [h(g(x))f(x)]. The dependency function h(g) expresses the node, f(x), in terms of {gi}.
Solution:
Prove the corresponding SAT problem “unsatisfiable”
Derive unsatisfiability proof [Goldberg/Novikov, DATE’03]
Derive interpolant from the unsatisfiability proof using McMillan’s procedure [CAV’03] (assume A and B as shown on previous slide)
Use interpolant as the dependency function, h(g)

15. Resynthesis Heuristics
Resynthesis is attempted for each node
Window, divisors, and resubstitution candidates are computed
Heuristics for different minimization criteria:
Area
Try replacing each fanin whose reference counter is 1
Net count
Try replacing each fanin
Delay
Try replacing each fanin that is on the critical path

16. Experimental Results Implementation of SAT-based resynthesis
ABC: Logic synthesis and verification system developed at UC Berkeley
SAT solver used is MiniSat-C_v by Niklas Een and Niklas Sörensson
Outline of experiments
Perform technology-independent synthesis: resyn; if
Perform high-quality FPGA mapping: if
Perform resynthesis
without choices: imfs –W 66; imfs –a –W 66; imfs -W 66
with choices (script is more complicated)
Measure gain in area, delay, net count
Commands used in the scripts
if is a new efficient FPGA mapper based on priority cuts
imfs is the new logic optimization and resynthesis engine described in the present paper,
resyn is a fast logic synthesis script that performs 5 iterations of AIG rewriting,
choice is a logic synthesis script that performs 15 passes of AIG rewriting and collects three snapshots of the current network: the original, the final, and an intermediate AIG saved after the first 5 rewriting passes.
Computer used ?
Runtime is several minutes for the largest designs in the tables

17. Resynthesis without Choices (K = 6)

18. Resynthesis with Choices (K = 6)

19. Academic Benchmarks

20. Academic Benchmarks (PLAs)

21. Conclusion Introduced and motivated resynthesis after mapping
Proposed a new SAT-based solution
uses SAT solver for all aspects of functional manipulation
uses rugged windowing scheme without previous limitations
designed for scalability and applicable to large industrial circuits
Showed promising experimental results
reduction: % of area, 0-3% in delay, % in net count
improvements are modest, but on top of a very strong synthesis
more substantial improvements on academic benchmarks
Future work
improving quality by implementing better candidate selection
improving runtime by fine-tuning simulation and SAT
customizing the package for timing-driven resynthesis and rewiring after placement
global circuit restructuring using interpolation

22. The End

23. Potential Applications
Technology-dependent
Resynthesis for LUTs and standard-cells to improve area, delay, power, the number of nets, etc
Timing-driven resynthesis and rewiring after placement
Technology-independent
optimization of logic networks to minimize number of factored form literals
optimization for AIGs to minimize AIG nodes (and record choices)

24. Algorithm Overview nodeSatBasedResynthesis( node, parameters ) {
window = nodeWindow( node, parameters );
divisors = nodeDivisors( node, window, parameters );
cands = nodeResubCandsFilter( node, window, parameters );
best_cand = NULL;
for each candidate set c in cands
if ( best_cand != NULL && resubCost(best_cand) < resubCost(c) )
continue;
if ( !resubFeasible( node, window, c ) )
best_cand = c; }
if ( best_cand != NULL ) {
best_func = nodeInterpolate( sat_solver, node );
nodeUpdate( node, best_cand, best_func );

25. Previous Work Optimization and mapping with internal flexibilities
S. Muroga, Y. Kambayashi, H. C. Lai, and J. N. Culliney, “The transduction method-design of logic networks based on permissible functions”, IEEE Trans. Comp, Vol.38(10), pp , Oct 1989
H. Savoj. Don't cares in multi-level network optimization. Ph.D. Dissertation, UC Berkeley, May 1992.
V. N. Kravets and P. Kudva, “Implicit enumeration of structural changes in circuit optimization”, Proc. DAC ’04, pp
A. Mishchenko and R. Brayton, "SAT-based complete don't-care computation for network optimization", Proc. DATE '05, pp
K. McMillan, “Don't-care computation using k-clause approximation”, Proc. IWLS ’05, pp
Equivalence under don’t-cares
Q. Zhu, N. Kitchen, A. Kuehlmann, and A. L. Sangiovanni-Vincentelli. "SAT sweeping with local observability don't-cares," Proc. DAC ’06, pp
S. Plaza, K.-H. Chang, I. L. Markov, and V. Bertacco, “Node mergers in the presence of don't cares'', Proc. ASP-DAC’07, pp
Maximal reduction resynthesis without don’t-cares
K.-C. Chen and J. Cong, “Maximal reduction of lookup-table-based FPGAs”, Proc. DATE ’92, pp
Computing dependency functions using interpolation
C.-C. Lee, J.-H. R. Jiang, C.-Y. Huang, and A. Mishchenko. “Scalable exploration of functional dependency by interpolation and incremental SAT solving”, Proc. IWLS’07.