1. CPRE 583 Reconfigurable Computing (VHDL Overview )
Instructor: Dr. Phillip Jones
Reconfigurable Computing Laboratory
Iowa State University
Ames, Iowa, USA

2. VHDL basics VHDL: (V)HSIC (H)ardware (D)escription (L)anguage
VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit
It is NOT a programming language!!!
It is a Hardware Description Language (HDL)
Conceptually VERY different form C,C++

3. Some Key Differences from C
C is inherently sequential (serial), one statement executed at a time
VHDL is inherently concurrent (parallel), many statements execute (simulate) at a time

4. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

5. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
Current Values:
A = 2
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

6. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 1
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

7. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

8. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1
Show impact
Of changing
Order of statements

9. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
Snap shot after input change
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

10. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 2

11. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 2
Different

12. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
Snap shot after input change
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 2

13. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 2

14. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4

15. Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”

16. Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
B(1) +
A(1)
C(1) +
Ans(1)
Y(1) +
X(1)
Z(1)

17. Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
B(1) +
A(2)
C(1) +
Ans(2)
Y(1) +
X(2)
Z(1)

18. Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
B(1) +
A(2)
C(1) +
Ans(4)
Y(1) +
X(2)
Z(1)

19. Corresponding circuit (More realistic)
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C after 2ns
X <= Y + Z after 2ns
Ans <= A + X after 2ns
“Simulates in parallel ever delta time step”
B(1) +
A(1)
C(1)
2ns +
Ans(1)
Y(1) +
2ns
X(1)
Z(1)
2ns

20. Corresponding circuit (More realistic)
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C after 2ns
X <= Y + Z after 2ns
Ans <= A + X after 2ns
“Simulates in parallel ever delta time step”
B(1) +
A(2)
C(1)
2ns +
Ans(2)
Y(1) +
2ns
X(2)
Z(1)
2ns

21. Corresponding circuit (More realistic)
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C after 2ns
X <= Y + Z after 2ns
Ans <= A + X after 2ns
“Simulates in parallel ever delta time step”
B(1) +
A(2)
C(1)
2ns +
Ans(4)
Y(1) +
2ns
X(2)
Z(1)
2ns

22. Typical Structure of a VHDL File
LIBRARY ieee;
ENTITY test_circuit IS
PORT(B,C,Y,Z,Ans);
END test_circuit;
ARCHITECTURE structure OF test_circuit IS
signal A : std_logic_vector(7 downto 0);
signal X : std_logic_vector(7 downto 0);
BEGIN
A <= B + C;
X <= Y + Z;
Ans <= A + X;
END
Include Libraries
Define component name and
Input/output ports
Declare internal
signals,
components
Implement components
functionality

23. Process
Process provide a level serialization in VHDL (e.g. variables, clocked processes)
Help separate and add structure to VHDL design

24. Process Example BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin
Ans <= A + X;
End My_process_1;
My_process_2 : process (B,X,Y,Ans1)
A <= B + 1;
X <= B + Y;
Ans2 <= Ans1 + X;
End My_process_2;
END;
Sensitivity list: specify inputs to the
process. Process is updated when
a specified input changes

25. Process Example (Multiple Drivers)
BEGIN
My_process_1 : process (A,B,C,X,Y,Z)
Begin
A <= B + C;
X <= Y + Z;
Ans <= A + X;
End My_process_1;
My_process_2 : process (B,X,Y,Ans1)
A <= B + 1;
X <= B + Y;
Ans2 <= Ans1 + X;
End My_process_2;
END;
A signal can only be
Driven (written) by one
process. But can be read
by many
Compile or simulator may
give a “multiple driver” Error
or Warning message

26. Process Example (Multiple Drivers)
BEGIN
My_process_1 : process (A,B,C,X,Y,Z)
Begin
A <= B + C;
X <= Y + Z;
Ans <= A + X;
End My_process_1;
My_process_2 : process (B,X,Y,Ans1)
A1 <= B + 1;
X1 <= B + Y;
Ans2 <= Ans1 + X;
End My_process_2;
END;
Maybe A,X were suppose to be A1,X1. Cut
and paste error. Or may need to rethink
Hardware structure to remove multiple driver
issue.

27. Process Example (if-statement)
BEGIN
My_process_1 : process (A,B,C,X,Y,Z)
Begin
if (B = 0) then
C <= A + B;
Z <= X + Y;
Ans1 <= A + X;
else
C <= 1;
Z <= 0;
Ans1 <= 1;
end if;
End My_process_1;
END;
Add circuit

28. Clock Process Example or and or BEGIN My_process_1 : process (clk)
IF (clk’event and clk = ‘1’) THEN
C <= A or B;
Z <= X or Y;
Ans <= C and Z;
END IF;
End My_process_1;
END;
circuit not clocked
A() or
C()
B()
and
Ans()
X() or
Z()
Y()

29. Clock Process Example or and or BEGIN My_process_1 : process (clk)
IF (clk’event and clk = ‘1’) THEN
C <= A or B;
Z <= X or Y;
Ans <= C and Z;
END IF;
End My_process_1;
END;
D Flip-Flop
DFF
Register
circuit with clock
A() or
C()
B()
and
Ans()
X() or
Z()
Y()
clk

30. Clock Process Example or and or BEGIN My_process_1 : process (clk)
IF (clk’event and clk = ‘1’) THEN
C <= A or B;
Z <= X or Y;
Ans <= C and Z;
END IF;
End My_process_1;
END;
circuit with clock
A() or
C()
B()
Ans()
and
X() or
Z()
Y()
clk

31. Clock Process Example 2 xor xor or BEGIN My_process_1 : process (clk)
IF (clk’event and clk = ‘1’) THEN
C <= A xor B;
Z <= X or Y;
Ans <= C xor Z;
END IF;
End My_process_1;
END;
circuit with clock
A()
xor
C()
B()
Ans()
xor
X() or
Z()
Y()
clk

32. Clock Process Example 2 (Answer)
BEGIN
My_process_1 : process (clk)
Begin
IF (clk’event and clk = ‘1’) THEN
C <= A xor B;
Z <= X or Y;
Ans <= C xor Z;
END IF;
End My_process_1;
END;
circuit with clock
A()
xor
C()
B()
Ans()
xor
X() or
Z()
Y()
clk

33. VHDL Constructs Entity Process Signal, Variable, Constants, Integers
Array, Record
VHDL on-line tutorials:

34. Signals and Variables Signals Updated at the end of a process
Have file scope
Variables
Updated instantaneously
Have process scope
VHDL on-line tutorials:

35. std_logic, std_logic_vector
Very common data types
std_logic
Single bit value
Values: U, X, 0, 1, Z, W, H, L, -
Example: signal A : std_logic;
A <= ‘1’;
Std_logic_vector: is an array of std_logic
Example: signal A : std_logic_vector (4 downto 0);
A <= x“00Z001”
VHDL on-line tutorials:

36. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’
Time step 0

37. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’ 1 U U U
Time step 0

38. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’ 1 U U
Time step 1

39. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’ 1 1 U
Time step 2

40. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’ 1 1 1
Time step 3

41. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’ 1 1 1 X 1
Time step 3

42. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’ 1 1 1 X 1 1
Time step 3

43. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’ 1 1 1 X X X 1
Time step 3

44. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’
‘1’
Pull-up resistor
Time step 0

45. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’
‘1’
Pull-up resistor U H U
Time step 0

46. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’
‘1’
Pull-up resistor 1 H 1
Time step 1

47. Std_logic values Std_logic values
U : Uninitialized (signal has not been assigned a value yet)
X : Unknow (2 drivers one ‘0’ one ‘1’)
H : weak ‘1’ (example: model pull-up resister)
I have never used this value
L : weak ‘0’
‘1’
Pull-up resistor
Resolution(H,0) = 0 1 1
Time step 2

48. Pre-defined VHDL attributes
mysignal’event (mysignal changed value)
mysignal’high (highest value of mysignal’s type)
mysignal’low
Many other attributes

49. Singal vs Varible scope
Signal: global to file
Variable: local to process
My_process_1 : process (B,C,Y)
Begin
A <= B + C;
Z <= Y + C;
End My_process_1;
My_process_2 : process (B,X,Y,Ans1)
X <= Z + 1;
Ans <= B + Y;
End My_process_2;
VHDL on-line tutorials:

50. Singal vs Varible scope
Signal: global to file
Variable: local to process
My_process_1 : process (B,C,Y)
Begin
A <= B + C;
varZ <= Y + C;
End My_process_1;
My_process_2 : process (B,X,Y,Ans1)
X <= varZ + 1;
Ans <= B + Y;
End My_process_2;
Each varZ are local
to their process.
Completely independent
VHDL on-line tutorials:

51. Arrays and Records Arrays: Group signals of the same type together
Records: Group signal of different types together
VHDL on-line tutorials:

52. Array Example (Delay Shift Register)
flag_in
flag_1
flag_2
flag_3
flag_out
BEGIN
My_process_1 : process (clk)
Begin
IF (clk’event and clk = ‘1’) THEN
flag_1 <= flag_in;
flag_2 <= flag_1;
flag_3 <= flag_2;
END IF;
End My_process_1;
flag_out <= flag_3
END;
VHDL on-line tutorials:

53. Array Example (Delay Shift Register)
flag_in
flag_1
flag_20
flag_out
type flag_reg_array is array (DELAY-1 downto 0) of std_logic;
signal flag_reg : flag_reg_array;
BEGIN
My_process_1 : process (clk)
Begin
IF (clk’event and clk = ‘1’) THEN
flag_reg(flag_reg'high downto 0) <=
flag_reg(flag_reg'high-1 downto 0) & flag_in;
END IF;
End My_process_1;
flag_out <= flag_reg(flag_reg'high);
END;

54. Array Example (Delay Shift Register)
flag_in
flag_1
flag_20
flag_out
BEGIN
My_process_1 : process (clk)
Begin
IF (clk’event and clk = ‘1’) THEN
flag_1 <= flag_in;
flag_2 <= flag_1;
flag_20 <= flag_19;
END IF;
End My_process_1;
flag_out <= flag_20
END;
VHDL on-line tutorials:

55. Array Example (Delay Shift Register)
flag_reg(flag_reg'high downto 0)<= flag_reg(flag_reg'high-1 downto 0) & flag_in;
flag_in
flag(0)
flag(1)
flag(2)
flag_out 1 1
flag_in
flag(0)
flag(1)
flag(2)
flag_out 1 1
flag_in
flag(0)
flag(1)
flag(2)
flag_out 1

56. Array Example (Delay Shift Register)
flag_in
flag_0
flag_1
flag_2
flag_out
BEGIN
My_process_1 : process (clk)
Begin
IF (clk’event and clk = ‘1’) THEN
flag_1 <= flag_in;
flag_2 <= flag_1;
flag_3 <= flag_2;
END IF;
End My_process_1;
flag_out <= flag_3
END;
VHDL on-line tutorials:

57. Finite State Machine (FSM) Design
Model of computation
High level application example (Networking)
Two major types
Moore
Mealy
Detailed view of application example

58. Finite State Machines What types of applications are they well suited
Streaming pattern recognition
Sequential event based control logic
Allow hardware designer to reason about things in small pieces

59. Streaming Network application (MP1)
Process UDP packet headers (event driven)
Detect patterns in payload (e.g. “Corn”)
Modify payload based on header information
FSM

60. Streaming Network application (MP1)
Process UDP packet headers (event driven)
Detect patterns in payload (e.g. “Corn”)
Modify payload based on header information
FSM
IP src

61. Streaming Network application (MP1)
Process UDP packet headers (event driven)
Detect patterns in payload (e.g. “Corn”)
Modify payload based on header information
FSM
IP dest
IP src

62. Streaming Network application (MP1)
Process UDP packet headers (event driven)
Detect patterns in payload (e.g. “Corn”)
Modify payload based on header information
FSM
src port
IP dest
IP src

63. Streaming Network application (MP1)
Process UDP packet headers (event driven)
Detect patterns in payload (e.g. “Corn”)
Modify payload based on header information
FSM
dest port
src port
IP dest
IP src

64. Streaming Network application (MP1)
Process UDP packet headers (event driven)
Detect patterns in payload (e.g. “Corn”)
Modify payload based on header information
FSM
length
dest port
src port
IP dest
IP src

65. Streaming Network application (MP1)
Process UDP packet headers (event driven)
Detect patterns in payload (e.g. “Corn”)
Modify payload based on header information
FSM
Data 1
length
dest port
src port
IP dest
IP src

66. Streaming Network application (MP1)
Process UDP packet headers (event driven)
Detect patterns in payload (e.g. “Corn”)
Modify payload based on header information
FSM
Data 2
Data 1
length
dest port
src port
IP dest
IP src

67. Streaming Network application (MP1)
Process UDP packet headers (event driven)
Detect patterns in payload (e.g. “Corn”)
Modify payload based on header information
FSM
Data 3
Data 2
Data 1
length
dest port
src port
IP dest

68. Streaming Network application (MP1)
Process UDP packet headers (event driven)
Detect patterns in payload (e.g. “Corn”)
Modify payload based on header information
FSM
Send Alert
Data 3
Data 2
Data 1
length
dest port
src port
IP dest

69. Streaming Network application (MP1)
Process UDP packet headers (event driven)
Detect patterns in payload (e.g. “Corn”)
Modify payload based on header information
FSM
Send Alert r o C
length
dest port
src port
IP dest

70. Streaming Network application (MP1)
Process UDP packet headers (event driven)
Detect patterns in payload (e.g. “Corn”)
Modify payload based on header information
FSM
Send Alert n r o C
length
dest port
src port

71. Streaming Network application (MP1)
Process UDP packet headers (event driven)
Detect patterns in payload (e.g. “Corn”)
Modify payload based on header information
FSM
Send Alert
Alert!! ! n r o C
length
dest port

72. Streaming Network application (MP1)
Process UDP packet headers (event driven)
Detect patterns in payload (e.g. “Corn”)
Modify payload based on header information
FSM
Send Alert
Modify Packet ! n r o C
length
dest port

73. Moore and Mealy FSMs
Moore: Output is only a function of the current state
Mealy: Output is a function of the current state and input (“Mealy is more”)

74. Moore FSM Moore: Output is only a function of the current state
Example detect every occurrence of “1011”
State Name
Start
(0) 1
(0) 11
(0)
011
(0)
1011
(1)
FSM output

75. Moore FSM Moore: Output is only a function of the current state
Example detect every occurrence of “1011”
Where to go on a
given input 1
Start
(0) 1
(0) 11
(0)
011
(0)
1011
(1)

76. Moore FSM Moore: Output is only a function of the current state
Example detect every occurrence of “1011” 1
Start
(0) 1
(0) 11
(0)
011
(0)
1011
(1)
Input: 1
Output: 0

77. Moore FSM Moore: Output is only a function of the current state
Example detect every occurrence of “1011” 1 1 1
Start
(0) 1
(0) 11
(0)
011
(0)
1011
(1) 1 1
Input: 11011
Output: 00010

78. Moore FSM Moore: Output is only a function of the current state
Example detect every occurrence of “1010” 10
(0) 1
010
(0)
1010
(1) 1
Start
(0)
(0) 1 1 1 1

79. Mealy FSM Moore: Output a function of the current state, and input
Example detect every occurrence of “1011”
State Name 1 11
011
1011

80. Mealy FSM Moore: Output a function of the current state, and input
Example detect every occurrence of “1011”
Input
output
1/0 1 11
011
1011
0/0
Start

81. Mealy FSM Mealy: Output a function of the current state, and input
Example detect every occurrence of “1011”
1/0
1/0
0/0 1 11
011
1011
0/0
0/0
1/0
Start
1/1
0/0

82. FSM: General Circuit Architecture
Let:
X be inputs
Z be outputs
State(t) be the state of the FSM at the current time
State(t+1) be the next state of the FSM
δ be the transition between states
State(t+1) = δ(State(t), X)
Output
Moore: Z(State(t))
Mealy: Z(State(t), X)
x=1/z=0
1/0 S1 S2
0/1
z=0
0/0

83. FSM: General Circuit Architecture
Moore
Combinational Logic
Z(State(t))
Z(State(t),X)
Inputs: X
Outputs
Mealy
State Storage
DFF
Next State
State(t+1) =
δ(State(t), X)
State(t)
DFF

84. VHDL: IF and CASE constructs
IF THEN ELSE can be mapped to a 2:1 Multiplexer (Mux)
sel = b“0”
IF (sel = ‘0’) THEN
out_1 <= in_0;
ELSE
out_1 <= in_1
END IF;
x”C” 4
2:1
Mux
in_0 4
out_1
x”C” 4
x”D”
in_1

85. VHDL: IF and CASE constructs
Mapping a CASE statement to a 4:1 Mux
CASE sel is
WHEN “00” =>
out_1 <= in_0;
WHEN “01” =>
out_1 <= in_1;
WHEN “10” =>
out_1 <= in_2;
WHEN “11” =>
out_1 <= in_3
WHEN OTHERS =>
END CASE;
sel = b“10” 2
x”C” 4
in_0
4:1
Mux 4
x”D”
in_1 4
out_1
x”7” 4
x”7”
in_2 4
x”2”
in_3
Why do we need others here?

86. VHDL: IF and CASE constructs
Mapping a CASE statement to a 1:4 Decoder
CASE state is
WHEN state_1 =>
IF (sel = ‘0’) THEN
mux_out <= ‘1’;
ELSE
mux_out <= ‘0’;
END IF;
WHEN state_11 =>
-- similar code
WHEN state_011 =>
WHEN state_1011 =>
--similar code
END CASE; on
2:1
Mux
1:4
Decoder
out_0
off
2:1
Mux
out_1
“10” 2
state
off
2:1
Mux
out_2
out_3
off
2:1
Mux
Enumerated Type
State = {state_1, state_11, state_011, state_1011} =
{“00”, ”01”, ”10”, ”11”}

87. VHDL: IF and CASE constructs
Mapping a CASE statement to a 1:4 Decoder
CASE state is
WHEN state_1 =>
IF (sel = ‘0’) THEN
mux_out <= ‘1’;
ELSE
mux_out <= ‘0’;
END IF;
WHEN state_11 =>
-- similar code
WHEN state_011 =>
WHEN state_1011 =>
--similar code
END CASE; on
2:1
Mux
1:4
Decoder
out_0
off
2:1
Mux
out_1
“00” 2
state
off
2:1
Mux
out_2
out_3
off
2:1
Mux
Enumerated Type
State = {state_1, state_11, state_011, state_1011} =
{“00”, ”01”, ”10”, ”11”}

88. FSM: General Circuit Architecture
Moore
Combinational Logic
Z(State(t))
Z(State(t),X)
Inputs: X
Outputs
Mealy
State Storage
DFF
Next State
State(t+1) =
δ(State(t), X)
State(t)
DFF

89. VHDL for Mealy (“1011”) Example
-- Store the “state”
Update_State: process(clk)
begin
if(clk’event and clk=‘1’) then
state <= next_state;
end if;
end process Update_State;
state
next_state
DFF

90. VHDL for Mealy (“1011”) Example
-- Compute combinational logic
Combinational: process(x, state)
begin
case state is
when state_1 =>
if(x = ‘0’) then
z <= ‘0‘;
next_state <= state_1;
else
next_state <= state_11;
end if;
when state_11 =>
z <= ‘0’;
next_state <= state_011 ;
Compute output
Compute next_state
1/0
1/0
0/0 1 11
011
1011
0/0
0/0
1/0
Start
1/1
0/0

91. VHDL for Mealy (“1011”) Example
when state_011 =>
if(x = ‘0’) then
z <= ‘0‘;
next_state <= state_1011;
else
next_state <= state_011;
end if;
when state_1011 =>
z <= ‘0’;
next_state <= state_1;
z <= ‘1‘;
next_state <= state_11;
end case;
end process Combinational;
1/0
1/0
0/0 1 11
011
1011
0/0
1/0
1/1
0/0

92. Network Processing Example: UDP
UDP – User Datagram Protocol
Popular protocol for sending data over the internet (TCP is popular another protocol)
Typical encapsulated within IP (Internet Protocol)
UDP/IP
Gives no guarantee of delivery
Relies on application layer to implement reliability
Unlike TCP which has reliably delivery build in.
Reference for more info on IP and UDP details
RCFs
Course

93. Destination IP Address
UDP/IP Packet Format
Ver
IHL
TOS
Total Length
Note: flags 3 bits
Identification
flags
fragment offset
IP Header
UDP Protocol = 17
TTL
Protocol
Header Checksum
Source IP Address
Destination IP Address
Options
Padding
Source Port
Destination Port
UDP Header
UDP length (bytes) =
UDP header+payload
Length
Checksum
Byte1
Byte2
Byte3
Byte4
Payload 31
32-bits

94. Example: Network Processing Tasks
Raise an alert signal when the pattern “corn!” is detected
Return the number of times “corn!” is detected
Place count value as the last byte of the payload

95. Streaming Network application (MP1)
Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload
FSM
Send Alert
Modify Packet ! n r o C
length
dest port

96. Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload
Draw out logic, and data flow!!!
Alert FSM
Alert
Register & Counter
Management
Packet Length
output
sel
position
corn_cnt
Packet Input
Process
2:1
Mux
Packet Output
Process

97. Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload
Alert FSM
Alert
Register & Counter
Management
Packet Length
output
sel
position
corn_cnt
Packet Input
Process
2:1
Mux
Packet Output
Process

98. Alert FSM Design Alert signal when the pattern “corn!” is detected
Z = {Alert}
“c”/0
“o”/0
“r”/0
“n”/0 c o r n !
others/0
Start
others/0
others/0
others/0
“!”/1

99. Alert FSM Design Alert signal when the pattern “corn!” is detected
Output Packet’s Length
Z = {Alert,length_vld,pack_length}
X = {vld,input} : Note “?” is don’t care
“c”/0
“o”/0
“r”/0
“n”/0 c o r n !
others/0
Start
others/0
others/0
others/0
“!”/1

100. Alert FSM Design Alert signal when the pattern “corn!” is detected
Output Packet’s Length
Z = {Alert,length_vld,pack_length}
X = {vld,input} : Note “?” is don’t care
UDP
ports
1,“c”/0,0,0
1,“o”/0,0,0
1,“r”/0,0,0
1,“n”/0,0,0
1,”?”/0,0,0
1,”?”/0,0,0 c o r n !
IPH_5
UDP
length
1,others/0,0,0
1,”?”/0,1,length
IPH_2
1,others/0,0,0
1,others/0,0,0
1,”?”/0,0,0
1,others/0,0,0
Start IP
1,“!”/1,0,0
Start

101. Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload
Alert FSM
Alert
Register & Counter
Management
Packet Length
output
sel
position
corn_cnt
Packet Input
Process
2:1
Mux
Packet Output
Process

102. Register & Counter Manager
Register & Counter Components
Design of Manager

103. Register and Counter Components
reset
load
sel(reset,load)
set_value
3:1
Mux 8
reg_val 8
DFF
Counter
reset
load
inc
sel(reset,load,inc)
set_value
4:1
Mux
count 8 8 + 8
inc_val
DFF

104. Practice: Write VHDL(process for each)
Register
Name : process(clk)
begin
if(clk’event and clk=‘1’) then
logic here
end if;
end process Name
reset
load
sel(reset,load)
3:1
Mux
reg_val
set_value 8 8
DFF
CASE sel is
WHEN “00” | “11”=>
out_1 <= in_0;
WHEN “01” =>
out_1 <= in_1;
WHEN OTHERS =>
END CASE;
Counter
reset
load
inc
sel(reset,load,inc)
set_value
4:1
Mux
count 8 8 + 8
inc_val
DFF

105. Register VHDL Name : process(clk) begin if(clk’event and clk=‘1’) then
CASE reset&load is
WHEN “10” | “11” =>
reg_val <= 0;
WHEN “01” =>
reg_val <= set_value;
WHEN OTHERS =>
reg_val <= reg_val;
END CASE;
end if;
end process Name
Register
reset
load
sel(reset,load)
set_value
3:1
Mux 8
reg_val 8
DFF

106. Register VHDL Name : process(clk) begin if(clk’event and clk=‘1’) then
CASE sel is
WHEN “10” | “11” =>
reg_val <= 0;
WHEN “01” =>
reg_val <= set_value;
WHEN OTHERS =>
reg_val <= reg_val;
END CASE;
end if;
end process Name
sel <= reset&load;
Register
reset
load
sel(reset,load)
set_value
3:1
Mux 8
reg_val 8
DFF

107. Counter VHDL + Name : process(clk) begin
if(clk’event and clk=‘1’) then
CASE reset&load&inc is
WHEN “100” | “101” |
“110”| “111” =>
count <= 0;
WHEN “010” | “011” =>
count <= set_value;
WHEN “001” =>
count <= count + inc_val;
WHEN OTHERS =>
count <= count;
END CASE;
end if;
end process Name
Counter
reset
load
inc
sel(reset,load,inc)
set_value
4:1
Mux
inc_val
count 8 8 + 8
DFF

108. Counter VHDL + Name : process(clk) begin
if(clk’event and clk=‘1’) then
CASE sel is
WHEN “100” | “101” |
“110”| “111” =>
count <= 0;
WHEN “010” | “011” =>
count <= set_value;
WHEN “001” =>
count <= count + inc_val;
WHEN OTHERS =>
count <= count;
END CASE;
end if;
end process Name
sel <= reset&load&inc;
Counter
reset
load
inc
sel(reset,load,inc)
set_value
4:1
Mux
inc_val
count 8 8 + 8
DFF

109. Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload
Alert FSM
Alert
Register & Counter
Management
Packet Length
output
sel
position
corn_cnt
Packet Input
Process
2:1
Mux
Packet Output
Process

110. Register and Counter Manger
Alert
inc
corn_cnt
Counter
inc_val 1
load
set_value
reset
reset
inc
position
Valid_data
Counter
inc_val 1
load
set_value
reset
reset
length_vld
load
Register
Packet_Length_reg
Packet_Length
set_value

111. Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload
Alert
Alert FSM
Register & Counter
Management
Packet Length
reset
length_vld
reset
position
output
sel
Packet_length
data
data_vld
corn_cnt
Packet Input
Process
2:1
Mux
Packet Output
Process

112. Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload
Alert
Alert FSM
Register & Counter
Management
Packet Length
reset
length_vld
reset
position
output
sel
Packet_length
data
data_vld
corn_cnt
Packet Input
Process
2:1
Mux
Packet Output
Process

113. Output sel Comparator outputs 1 if inputs match Packet_length
Position
sel
corn_cnt 1
2:1
Mux
Data_to_output
Data_from_input

114. Output sel: VHDL NOT in a process!
Data_to_output <= corn_cnt when (Packet_length = Position)
else Data_from_input
Comparator outputs 1 if inputs match
Packet_length
Comparator
Position
sel
corn_cnt 1
2:1
Mux
Data_to_output
Data_from_input

115. Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload
Alert
Alert FSM
Register & Counter
Management
Packet Length
reset
length_vld
reset
position
output
sel
Packet_length
data
data_vld
corn_cnt
Packet Input
Process
2:1
Mux
Packet Output
Process

116. Multiple Characters per Clock
Network input stream typically 32-bit words
4 8-bit characters per word.
corn! Example c o r n
Word 1 ! ? ? ?
Word 2
corn/0
Start
corn
!???
Corn! on a word boundary
others/0
!???/1

117. Multiple Characters per Clock
Network input stream typically 32-bit words
4 8-bit characters per word.
corn! Example ? c o r
Word 1 n ! ? ?
Word 2
?cor/0
Start
?cor
n!??
Corn! offset by 1 byte
others/0
n!??/1

118. Multiple Characters per Clock
Network input stream typically 32-bit words
4 8-bit characters per word.
corn! Example ? ? c o
Word 1 r n ! ?
Word 2
??co/0
Start
??co
rn!?
Corn! offset by 2 bytes
others/0
rn!/1

119. Multiple Characters per Clock
Network input stream typically 32-bit words
4 8-bit characters per word.
corn! Example ? ? ? c
Word 1 o r n !
Word 2
???c/0
Start
???c
orn!
Corn! offset by 3 bytes
others/0
orn!/1

120. Multiple Characters per Clock
Network input stream typically 32-bit words
4 8-bit characters per word.
corn! Example c o r n
Word 2 ! ? ? ?
Word 3
corn/0
Start
corn
!???
Corn! offset by 4 bytes
others/0
!???/1

121. Modify Alert FSM for Multiple characters
Start

122. Modify Alert FSM for Multiple characters
Start
?cor/0
???c/0
?cor
n!??
???c
orn!
corn/0
??co/0
corn
!???
??co
rn!?
others/0
others/0
n!??/1
orn!/1
others/0
others/0
!???/1
rn!/1

123. Modify Alert FSM for Multiple characters
Start
?cor/0
???c/0
?cor
n!??
???c
orn!
corn/0
??co/0
corn
!???
??co
rn!?
others/0
others/0
n!??/1
orn!/1
others/0
others/0
!???/1
rn!/1

124. Modify Alert FSM for Multiple characters
Start
?cor/0
Start
???c/0
Start
Start
?cor
n!??
???c
orn!
??co/0
corn/0
??co
rn!?
corn
!???
others/0
others/0
n!??/1
orn!/1
others/0
others/0
!???/1
rn!?/1

125. Modify Alert FSM for Multiple charactersb c o r n ! c o r n ! z c o r
Start
?cor/0
Start
???c/0
Start
Start
?cor
n!??
???c
orn!
??co/0
corn/0
??co
rn!?
corn
!???
others/0
others/0
n!??/1
orn!/1
others/0
others/0
!???/1
rn!?/1

126. Modify Alert FSM for Multiple charactersb c o r n ! c o r n ! z c o r
Start
?cor/0
Start
???c/0
Start
Start
?cor
n!??
???c
orn!
??co/0
corn/0
??co
rn!?
corn
!???
others/0
others/0
n!??/1
orn!/1
others/0
others/0
!???/1
rn!?/1

127. Modify Alert FSM for Multiple charactersb c o r n ! c o r n ! z c o r
Start
?cor/0
Start
???c/0
Start
Start
?cor
n!??
???c
orn!
??co/0
corn/0
??co
rn!?
corn
!???
others/0
others/0
n!??/1
orn!/1
others/0
others/0
!???/1
rn!?/1

128. Modify Alert FSM for Multiple charactersb c o r n ! c o r n ! z c o r
Start
?cor/0
Start
???c/0
Start
Start
?cor
n!??
???c
orn!
??co/0
corn/0
??co
rn!?
corn
!???
others/0
others/0
n!??/1
orn!/1
others/0
others/0
!???/1
rn!?/1

129. Modify Alert FSM for Multiple charactersb c o r n ! c o r n ! z c o r
Start
?cor/0
Start
???c/0
Start
Start
?cor
n!??
???c
orn!
??co/0
corn/0
??co
rn!?
corn
!???
others/0
others/0
n!??/1
orn!/1
others/0
others/0
!???/1
rn!?/1

130. Modify Alert FSM for Multiple charactersb c o r n ! c o r n ! z c o r
Start
?cor/0
Start
???c/0
Start
Start
?cor
n!??
???c
orn!
??co/0
corn/0
??co
rn!?
corn
!???
others/0
others/0
n!??/1
orn!/1
others/0
others/0
!???/1
rn!?/1

131. Modify Alert FSM for Multiple charactersb c o r n ! c o r n ! z c o r
Start
?cor/0
Start
???c/0
Start
Start
?cor
n!??
???c
orn!
??co/0
corn/0
??co
rn!?
corn
!???
others/0
others/0
n!??/1
orn!/1
others/0
others/0
!???/1
rn!?/1

132. Modify Alert FSM for Multiple charactersb c o r n ! c o r n ! z c o r
Start
?cor/0
Start
???c/0
Start
Start
?cor
n!??
???c
orn!
??co/0
corn/0
??co
rn!?
corn
!???
others/0
others/0
n!??/1
orn!/1
others/0
others/0
!???/1
rn!?/1

133. Modify Alert FSM for Multiple charactersb c o r n ! c o r n ! z c o r
Start
?cor/0
Start
???c/0
Start
Start
?cor
n!??
???c
orn!
??co/0
corn/0
??co
rn!?
corn
!???
others/0
others/0
n!??/1
orn!/1
others/0
others/0
!???/1
rn!?/1

134. Modify Alert FSM for Multiple charactersb c o r n ! c o r n ! z c o r
Start
?cor/0
Start
???c/0
Start
Start
?cor
n!??
???c
orn!
??co/0
corn/0
??co
rn!?
corn
!???
others/0
others/0
n!??/1
orn!/1
others/0
others/0
!???/1
rn!?/1

135. Modify corn! counter for Multiple characters
Alert
inc
Counter
corn_cnt
inc_val 1
load
set_value
reset
reset

136. Modify corn! counter for Multiple characters
Alt_0
Alt_1
inc
Alt_2
Counter
Alt_3
corn_cnt
inc_val 1
load
set_value
reset
reset

137. Modify corn! counter for Multiple characters
Alt_0
Alt_1 OR
inc
Alt_2
Counter
Alt_3
corn_cnt
inc_val 1
load
set_value
reset
reset

138. Modify corn! counter for Multiple characters
Alt_0
Alt_1 OR
inc
Alt_2
Counter
Alt_3
sel(Alt0,Alt1,
Alt2,Alt3)
corn_cnt 1
inc_val
4:1
Mux 2
load 3 4
set_value
reset
reset
NOT in a process!
Alt_merge <= Alt0 & Alt1 & Alt2 & Alt3;
inc_val <= 4 when (Alt_merge = “1111”)
3 when (Alt_merge = “0111” or Alt_merge = “1011” ...)
2 when (Alt_merge = “0011” or Alt_merge = “0110” ...)
else 0

139. Modify corn! counter for Multiple characters
Alt_0
Alt_1 OR
inc
Alt_2
Counter
Alt_3
corn_cnt
inc_val 1
load
set_value
reset
reset

140. In progress Slides

141. Moore FSM Moore: Output is only a function of the current state
Example detect every occurrence of “1011”
State Name
Start
(0) 1
(0) 11
(0)
011
(0)
1011
(1)
FSM output

142. Moore FSM Moore: Output is only a function of the current state
Example detect every occurrence of “1011”
Where to go on a
given input 1
Start
(0) 1
(0) 11
(0)
011
(0)
1011
(1)

143. Moore FSM Moore: Output is only a function of the current state
Example detect every occurrence of “1011” 1
Start
(0) 1
(0) 11
(0)
011
(0)
1011
(1)
Input: 1

144. Moore FSM Moore: Output is only a function of the current state
Example detect every occurrence of “1011” 1 1
Start
(0) 1
(0) 11
(0)
011
(0)
1011
(1)
Input: 11

145. Moore FSM Moore: Output is only a function of the current state
Example detect every occurrence of “1011” 1 1
Start
(0) 1
(0) 11
(0)
011
(0)
1011
(1) 1
Input: 011

146. Moore FSM Moore: Output is only a function of the current state
Example detect every occurrence of “1011” 1 1 1
Start
(0) 1
(0) 11
(0)
011
(0)
1011
(1) 1
Input: 1011

147. Moore FSM Moore: Output is only a function of the current state
Example detect every occurrence of “1011” 1 1 1
Start
(0) 1
(0) 11
(0)
011
(0)
1011
(1) 1
Input: 01011

148. Moore FSM Moore: Output is only a function of the current state
Example detect every occurrence of “1011” 1 1 1
Start
(0) 1
(0) 11
(0)
011
(0)
1011
(1) 1 1
Input: 11011

149. Moore FSM Moore: Output is only a function of the current state
Example: vending machine
Events (assume all items cost 1 coin):
Insert Coin
Make selection
Make
selection
Insert Coin
Start
(0)
Coin
(0)
Snack
(1)
Insert Coin
Insert Coin
Return
(0)
Make
selection
Make
selection

150. Moore FSM Moore: Output is only a function of the current state
Example: vending machine
Events (assume all items cost 1 coin):
Insert Coin
Make selection
Return Coin
Make
selection
Insert Coin
Start
(0)
Coin
(0)
Snack
(1)
Insert Coin
Return
(0)
Make
selection
Return
Coin

151. Moore FSM Moore: Output is only a function of the current state
Example: vending machine
Events (assume all items cost 1 coin):
Insert Coin
Make selection
Return Coin
Make
selection
Insert Coin
Insert Coin
Start
(0)
Coin
(0)
Snack
(1)
Make
selection
Insert Coin
Return
coin
Return
(0)
Return
Coin
Make
selection
Return
Coin

152. Moore FSM Moore: Output is only a function of the current state
Example: vending machine
Events (assume all items cost 1 coin):
Insert Coin
Make selection
Make Coin
a snack option
Make
selection
Insert Coin
Start
(0)
Coin
(0)
Snack
(1)
Insert Coin
Insert Coin
Return
(0)
Make
selection
Make
selection