1. The University of Adelaide, School of Computer Science
Computer Architecture
A Quantitative Approach, Fifth Edition
The University of Adelaide, School of Computer Science
20 September 2018
Chapter 1
Fundamentals of Quantitative Design and Analysis
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

2. The University of Adelaide, School of Computer Science
20 September 2018
Computer Technology
Introduction
Performance improvements:
Improvements in semiconductor technology
Feature size, clock speed
Improvements in computer architectures
Enabled by HLL compilers, UNIX
Lead to RISC architectures
Together have enabled:
Lightweight computers
Productivity-based managed/interpreted programming languages
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

3. Single Processor Performance
Introduction
Move to multi-processor
RISC
Copyright © 2012, Elsevier Inc. All rights reserved.

4. Levels of Representation
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
High Level Language Program
Compiler
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
Assembly Language Program
Assembler
Machine Language Program
Machine Interpretation
Control Signal Specification
ALUOP[0:3] <= InstReg[9:11] & MASK

5. Instruction Set Architecture
... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation – Amdahl, Blaaw, and Brooks, 1964
SOFTWARE
-- Organization of Programmable
Storage
-- Data Types & Data Structures:
Encodings & Representations
-- Instruction Formats
-- Instruction (or Operation Code) Set
-- Modes of Addressing and Accessing Data Items and Instructions
-- Exceptional Conditions

6. Organization
Capabilities & Performance Characteristics of Principal Functional Units
(e.g., Registers, ALU, Shifters, Logic Units, ...)
Ways in which these components are interconnected
Information flows between components
Logic and means by which such information flow is controlled.
Choreography of FUs to realize the ISA
Register Transfer Level (RTL) Description
Logic Designer's View
ISA Level
FUs & Interconnect
Design state of art organization in 1990

7. Review: MIPS R3000 (core) r0 r1 ° r31 Programmable storage
Programmable storage
2^32 x bytes
31 x 32-bit GPRs (R0=0)
32 x 32-bit FP regs (paired DP)
HI, LO, PC
Data types ?
Format ?
Addressing Modes? PC lo hi
Arithmetic logical
Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU,
AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUI
SLL, SRL, SRA, SLLV, SRLV, SRAV
Memory Access
LB, LBU, LH, LHU, LW, LWL,LWR
SB, SH, SW, SWL, SWR
Control
J, JAL, JR, JALR
BEq, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL
32-bit instructions on word boundary

8. Types of Internal Storage
Stack, Accumulator, A Set of Registers

9. Review: Basic ISA Classes
Accumulator:
1 address add A acc ¬ acc + mem[A]
1+x address addx A acc ¬ acc + mem[A + x]
Stack:
0 address add tos ¬ tos + next
General Purpose Register:
2 address add A B EA(A) ¬ EA(A) + EA(B)
3 address add A B C EA(A) ¬ EA(B) + EA(C)
Load/Store:
load Ra Rb Ra ¬ mem[Rb]
store Ra Rb mem[Rb] ¬ Ra
Invented index register
Reverse polish stack = HP calculator
GPR = last 20 years
L/S variant = last 10 years

10. Instruction Formats … Addressing modes
Variable:
Fixed:
Hybrid:
Addressing modes
each operand requires addess specifier => variable format
code size => variable length instructions
performance => fixed length instructions
simple decoding, predictable operations
With load/store instruction arch, only one memory address and few addressing modes
=> simple format, address mode given by opcode

11. MIPS Addressing Modes & Formats
Simple addressing modes
All instructions 32 bits wide
Register (direct) op rs rt rd
register
Immediate op rs rt
immed
Base+index op rs rt
immed
Memory
register +
PC-relative op rs rt
immed
Memory PC +

12. Cray-1: the original RISC
Register-Register 15 9 8 6 5 3 2 Op Rd
Rs1 R2
Load, Store and Branch 15 9 8 6 5 3 2 15 Op Rd
Rs1
Immediate

13. VAX-11: the canonical CISC
Variable format, 2 and 3 address instruction
Rich set of orthogonal address modes
immediate, offset, indexed, autoinc/dec, indirect, indirect+offset
applied to any operand
Simple and complex instructions
synchronization instructions
data structure operations (queues)
polynomial evaluation

14. RISC vs. CISC Pipelining Ease of Hardware Implementation
Simple Instructions
Simple Addressing Mode
Fixed-Length Formats
Large Number of Registers
MIPS, …
Simple Compilers
Powerful Addressing Mode
Powerful Instructions
Efficient Instruction Encoding
Few Registers
VAX

15. Review: Load/Store Architectures
° no memory reference per ALU instruction
- 3 address GPR
° Register to register arithmetic
° Load and store with simple addressing modes (reg + immediate)
° Simple conditionals
compare ops + branch z
compare&branch
condition code + branch on condition
° Simple fixed-format encoding
MEM
reg op r r r op r r
immed op
offset

16. MIPS R3000 Instruction Set Architecture
R0 - R31 PC HI LO
Registers
Machine Environment Target
Instruction Categories
Load/Store
Computational
Jump and Branch
Floating Point (coprocessor)
3 Instruction Formats: all 32 bits wide R: OP Rs Rt Rd sa
funct
Immediate
jump target I: J:

17. Execution Cycle Obtain instruction from program storage Instruction
Fetch
Decode
Operand
Execute
Result
Store
Next
Obtain instruction from program storage
Determine required actions and instruction size
Locate and obtain operand data
Compute result value or status
Deposit results in storage for later use
Determine successor instruction

18. What’s a Clock Cycle? Old days: 10 levels of gates
Latch or
register
combinational
logic
Old days: 10 levels of gates
Today: determined by numerous time-of-flight issues + gate delays
clock propagation, wire lengths, drivers

19. Current Trends in Architecture
The University of Adelaide, School of Computer Science
20 September 2018
Current Trends in Architecture
Introduction
Cannot continue to leverage Instruction-Level parallelism (ILP)
Single processor performance improvement ended in 2003
New models for performance:
Data-level parallelism (DLP)
Thread-level parallelism (TLP)
Request-level parallelism (RLP)
These require explicit restructuring of the application
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

20. The University of Adelaide, School of Computer Science
20 September 2018
Classes of Computers
Classes of Computers
Personal Mobile Device (PMD)
e.g. start phones, tablet computers
Emphasis on energy efficiency and real-time
Desktop Computing
Emphasis on price-performance
Servers
Emphasis on availability, scalability, throughput
Clusters / Warehouse Scale Computers
Used for “Software as a Service (SaaS)”
Emphasis on availability and price-performance
Sub-class: Supercomputers, emphasis: floating-point performance and fast internal networks
Embedded Computers
Emphasis: price
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

21. The University of Adelaide, School of Computer Science
20 September 2018
Parallelism
Classes of Computers
Classes of parallelism in applications:
Data-Level Parallelism (DLP)
Task-Level Parallelism (TLP)
Classes of architectural parallelism:
Instruction-Level Parallelism (ILP)
Vector architectures/Graphic Processor Units (GPUs)
Thread-Level Parallelism
Request-Level Parallelism
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

22. The University of Adelaide, School of Computer Science
20 September 2018
Flynn’s Taxonomy
Classes of Computers
Single instruction stream, single data stream (SISD)
Single instruction stream, multiple data streams (SIMD)
Vector architectures
Multimedia extensions
Graphics processor units
Multiple instruction streams, single data stream (MISD)
No commercial implementation
Multiple instruction streams, multiple data streams (MIMD)
Tightly-coupled MIMD
Loosely-coupled MIMD
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

23. Defining Computer Architecture
The University of Adelaide, School of Computer Science
20 September 2018
Defining Computer Architecture
“Old” view of computer architecture:
Instruction Set Architecture (ISA) design
i.e. decisions regarding:
registers, memory addressing, addressing modes, instruction operands, available operations, control flow instructions, instruction encoding
“Real” computer architecture:
Specific requirements of the target machine
Design to maximize performance within constraints: cost, power, and availability
Includes ISA, microarchitecture, hardware
Defining Computer Architecture
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

24. The University of Adelaide, School of Computer Science
20 September 2018
Trends in Technology
Trends in Technology
Integrated circuit technology
Transistor density: 35%/year
Die size: %/year
Integration overall: %/year
DRAM capacity: %/year (slowing)
Flash capacity: %/year
15-20X cheaper/bit than DRAM
Magnetic disk technology: 40%/year
15-25X cheaper/bit then Flash
X cheaper/bit than DRAM
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

25. The University of Adelaide, School of Computer Science
20 September 2018
Bandwidth and Latency
Trends in Technology
Bandwidth or throughput
Total work done in a given time
10,000-25,000X improvement for processors
X improvement for memory and disks
Latency or response time
Time between start and completion of an event
30-80X improvement for processors
6-8X improvement for memory and disks
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

26. Copyright © 2012, Elsevier Inc. All rights reserved.
Bandwidth and Latency
Trends in Technology
Log-log plot of bandwidth and latency milestones
Copyright © 2012, Elsevier Inc. All rights reserved.

27. The University of Adelaide, School of Computer Science
20 September 2018
Transistors and Wires
Trends in Technology
Feature size
Minimum size of transistor or wire in x or y dimension
10 microns in 1971 to .032 microns in 2011
Transistor performance scales linearly
Wire delay does not improve with feature size!
Integration density scales quadratically
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

28. The University of Adelaide, School of Computer Science
20 September 2018
Power and Energy
Problem: Get power in, get power out
Thermal Design Power (TDP)
Characterizes sustained power consumption
Used as target for power supply and cooling system
Lower than peak power, higher than average power consumption
Clock rate can be reduced dynamically to limit power consumption
Energy per task is often a better measurement
Trends in Power and Energy
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

29. Dynamic Energy and Power
The University of Adelaide, School of Computer Science
20 September 2018
Dynamic Energy and Power
Dynamic energy
Transistor switch from 0 -> 1 or 1 -> 0
½ x Capacitive load x Voltage2
Dynamic power
½ x Capacitive load x Voltage2 x Frequency switched
Reducing clock rate reduces power, not energy
Trends in Power and Energy
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

30. The University of Adelaide, School of Computer Science
20 September 2018
Power
Intel consumed ~ 2 W
3.3 GHz Intel Core i7 consumes 130 W
Heat must be dissipated from 1.5 x 1.5 cm chip
This is the limit of what can be cooled by air
Trends in Power and Energy
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

31. The University of Adelaide, School of Computer Science
20 September 2018
Reducing Power
Techniques for reducing power:
Do nothing well
Dynamic Voltage-Frequency Scaling
Low power state for DRAM, disks
Overclocking, turning off cores
Trends in Power and Energy
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

32. The University of Adelaide, School of Computer Science
20 September 2018
Static Power
Static power consumption
Currentstatic x Voltage
Scales with number of transistors
To reduce: power gating
Trends in Power and Energy
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

33. Example of Quantifying Power
Suppose 15% reduction in voltage results in a 15% reduction in frequency. What is impact on dynamic power?
9/20/2018

34. Example of Quantifying Power
Suppose 15% reduction in voltage results in a 15% reduction in frequency. What is impact on dynamic power?
9/20/2018

35. Copyright © 2012, Elsevier Inc. All rights reserved.
Example
Your company’s internal studies show that a single-core system is sufficient for the demand on your processing power; however, you are exploring whether you could save power by using two cores. (P = CV2F)
a) Assume that your application is 90% parallelizable. By how much could you decrease the frequency and get the same performance? 
b) Assume that the voltage may be decreased linearly with the frequency. How much dynamic power would the dual-core system require as compared to the single-core system?
Copyright © 2012, Elsevier Inc. All rights reserved.

36. Trends in Cost (no test)
The University of Adelaide, School of Computer Science
20 September 2018
Trends in Cost (no test)
Trends in Cost
Cost driven down by learning curve
Yield
DRAM: price closely tracks cost
Microprocessors: price depends on volume
10% less for each doubling of volume
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

37. Integrated Circuit Cost
The University of Adelaide, School of Computer Science
20 September 2018
Integrated Circuit Cost
Trends in Cost
Integrated circuit
Bose-Einstein formula:
Defects per unit area = defects per square cm (2010)
N = process-complexity factor = (40 nm, 2010)
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

38. The University of Adelaide, School of Computer Science
20 September 2018
Dependability
Dependability
Module reliability
Mean time to failure (MTTF)
Mean time to repair (MTTR)
Mean time between failures (MTBF) = MTTF + MTTR
Availability = MTTF / MTBF
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

39. Copyright © 2012, Elsevier Inc. All rights reserved.
Example
Calculate MTTF of a disk subsystem with
10 disks, each rated at 1,000,000 hour MTTF
1 SCSI controller, 500,000 hour MTTF
1 power supply, 200,000 hour MTTF
1 fan, 200,000 MTTF
1 SCSI cable, 1,000,000 hour MTTF
Copyright © 2012, Elsevier Inc. All rights reserved.

40. Measuring Performance
The University of Adelaide, School of Computer Science
20 September 2018
Measuring Performance
Typical performance metrics:
Response time
Throughput
Speedup of X relative to Y
Execution timeY / Execution timeX
Execution time
Wall clock time: includes all system overheads
CPU time: only computation time
Benchmarks
Kernels (e.g. matrix multiply)
Toy programs (e.g. sorting)
Synthetic benchmarks (e.g. Dhrystone)
Benchmark suites (e.g. SPEC06fp, TPC-C)
Measuring Performance
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

41. Principles of Computer Design
The University of Adelaide, School of Computer Science
20 September 2018
Principles of Computer Design
Principles
Take Advantage of Parallelism
e.g. multiple processors, disks, memory banks, pipelining, multiple functional units
Principle of Locality
Reuse of data and instructions
Focus on the Common Case
Amdahl’s Law
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

42. Principles of Computer Design
The University of Adelaide, School of Computer Science
20 September 2018
Principles of Computer Design
Principles
The Processor Performance Equation
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

43. Principles of Computer Design
The University of Adelaide, School of Computer Science
20 September 2018
Principles of Computer Design
Principles
Different instruction types having different CPIs
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer