1. Microprocessor and Assembly Language
Lecture-5-Addressing Modes
Muhammad Hafeez
Department of Computer Science
GC University Lahore

2. Today’s Agenda
Arrays
Addressing Modes

3. Declare An Array DUP Operator
Possible to define data, who elements share a common initial value
DATA1 DB 100 DUP(0)
DATA2 DB 50 DUP(?)
DATA3 DB 5,4,3 DUP(2,2 DUP(1),1)

4. Declare A Byte Array myArray DB 10H,20H,30H,40H
Assembly Address can also be written as myArray[0], myArray[1],…
Offset
Assembly Address
Value
0200
myArray
10h
0201
myArray+1
20h
0202
myArray+2
30h
0203
myArray+3
40H

5. Declare A Word Array myWordArray DW 10H,20H,30H,40H
Assembly Address can also be written as myWordArray[0], myWordArray[2],…
Offset
Assembly Address
Value
0200
myWordArray
10h
0202
myWordArray+2
20h
0204
myWordArray+4
30h
0206
myWordArray+6
40H

6. Location of Array Element
A is location of element
S is size of a particular element, for Byte S=1 for Word S=2
Position
Location 1 A 2
A = 1 x S 3
A = 2 X S 4
A = 3 X S N
A = (N-1) X S

7. Addressing Modes
We know nearly every instruction involves one or two operands.
We know the operands may be registers, immediate data, or memory operand.
Addressing modes describes the various ways through which programmer can access operands.
Addressing Mode particularly help in addressing memory location used in Array

8. Addressing Modes
Number of addressing modes is determined when the microprocessor is designed and cannot be changed.
Much of CPU power lies on its ability to handle large types of operands.
Effective Address of an operand refers to the distance of the data from the beginning of a segment.
Addressing modes are associated with types of operands

9. Addressing Modes
The Way an Operand’s Effective Address is specified is called Addressing Modes
The Operands can be specified using:
Register Addressing Mode
Immediate Addressing Mode
Direct Addressing Mode
Register Indirect Addressing Mode
Based Addressing Mode
Indexed Addressing Mode
Based Indexed Addressing Mode

10. Register Addressing Mode
Transfers a copy of a byte or word from the Source Register to the Destination Register.
Example: MOV AX,BX

11. Direct Addressing Mode
Moves a byte or word between a Memory Location and a Register. Instruction set does not support a memory to memory transfer.
Example:
MOV CX,List
Effective Address is generated as: DS * 10H
+ DISP(LIST)
MOV BX, myArray[0]
+ myArray + Disp

12. Register In-Direct Addressing Mode
The OFFSET of an operand is contained in a register
The Register could be BX, SI, DI and BP
What is the default segment registers of these offset registers?
Format is [register]
Suppose BX has value 0100H and this value is the address of a memory location that has content 1234H, then
MOV AX, [BX]
Will place 1234H in AX

13. Register In-Direct Addressing Mode
Some implementation of Register Indirect Addressing Mode
MOV AX,[BX]
MOV CX,[SI]
MOV [DI],[SI]
ADD DX,[DI]
Which instruction is illegal?

14. Example:
Add into AX, 10 elements of an array using Register Indirect Addressing Mode
MOV AX,0
LEA BX, LIST
MOV CX,10
ADDS:
ADD AX,[SI]
ADD SI,2
LOOP ADDS

15. Example:
Add into AX, 10 elements of an array using Register Indirect Addressing Mode
MOV AX,0
LEA BX, LIST
MOV CX,10
ADDS:
ADD AX,[SI]
ADD SI,2
LOOP ADDS

16. Based Addressing Mode/ Indexed Addressing Mode
Operand’s Offset address is obtained by adding a number called displacement into the content of a register
Displacement can be:
A constant (negative or positive)
Offset address of a variable
Offset address of a variable plus or minus a constant

17. Based Addressing Mode/ Indexed Addressing Mode
The Syntax can be:
[Register + Displacement]
[Displacement + Register]
Displacement + [Register]
[Register] + Displacement
Displacement [Register]
IF BP, BX is used Addressing Mode is called Based
If SI, DI is used Addressing Mode is called Indexed

18. Example: MOV CX,17 MOV SI,0 TOP: NEXT: INC SI LOOP TOP
Replace Lower Case String with upper case letter by letter.
MSG DB ‘lower case string’
MOV CX,17
MOV SI,0
TOP:
CMP MSG[SI],20H
JE NEXT
SUB MSG[SI],20H
NEXT:
INC SI
LOOP TOP

19. PTR Pseudo-Op Operands of the instructions must be of the same size
What about a constant moving into Register or Memory ?
When you want to store some constant into a memory location pointed by a register such as
MOV [SI], 5
It will not be assembled
REASON ??

20. PTR Pseudo-Op
The assembler will not know whether to move 5 into Byte of Memory of Word of Memory
If you want to move 5 into Byte of Memory then write
MOV Byte Ptr [SI],5
If you want to move 5 into Word of memory then write
MOV Word Ptr [SI],5

21. Two Dimensional Array
An Array whose elements are one dimensional arrays itself
Memory is sequential
Two Dimensional arrays are stored sequentially
Two Methods:
Row Major Order
Row0 is stored first, then row1 and so on
Column Major Order
Column0 is stored first then, then column1 and so on

22. Row Major Order / Column Major Order
Row Major Order: B[0,0],B[0,1],B[0,2],B[1,0],B[1,1],B[1,2],….
Column Major Order: B[0,0],B[1,0],B[2,0],B[0,1],B[1,1],B[2,1],….
Most High Level Languages store data in Row Major Order

23. Declare Two Dimensional Array in Assembly
Row Major Order
Array DB 10,20,30
DB 40,50,60
DB 70,80,90
Column Major Order
Array DB 10,40,70
DB 20,50,80
DB 30,60,90

24. Locate an Element in Two Dimensional Array
A [i,j] is MxN a 2D array, stored in Row Major Order
M is Total Number of rows
N is Total Number of columns
Where i is row number and j is column
Locate, where i begins
Find jth Column in that ith row

25. Locate an Element in Two Dimensional Array
Suppose S is the size of element, s=1 for byte array and s=2 for word array
Row0 begins at A
Row i begins at A+i*N*S where i is the row to find, N is total number of column in 2D array and S is the size of each element
jth element is stored at j*S bytes from start from row
So, A[i,j] location is A+(i*N+j)*S

26. Based Indexed Addressing Mode
The Effective Address of operand is found at the sum of
Contents of Based Register [BX OR BP]
Contents of Indexed Register [SI OR DI]
Optionally, a variable’s offset address
Optionally, a constant (positive or negative)

27. Based Indexed Addressing Mode
There are many valid ways to write Based Indexed Addressing Mode, some of them are
[base + index + variable + constant]<-- preferred
variable[base + index + constant]
constant[base + index + variable]

28. Example: Based Indexed Addressing Mode
Suppose A is a 5x7 word array stored in row-major order. Write code to clear row 2.
    MOV   BX,28       ; BX indexes row 2      MOV SI,0       ; SI will index columns      MOV   CX,7   ; # elements in a row clear:   
MOV   [BX + SI + A],0  ; clear A[2,j]      ADD   SI,2             ; go to next column      LOOP  clear            ; loop until done

29. Example: Based Indexed Addressing Mode
Another Example: Write code to clear column 3 -- Since A is a 7 column word array we need to add 2*7 = 14 to get to the next row
        mov   si,6       ; si indexes column 3          xor   bx,bx      ; bx will index rows          mov   cx,5      ; #elements in a column  clear:          mov   [bx + si + A],0   ; clear A[i,3]          add   bx,14             ; go to next row          loop  clear             ; loop until done

30. Questions
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