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Instruction Set Architectures
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Our Progress Done with levels 0 and 1
Seen multiple examples of level 2 Ready for ISA general principles
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Choices, choices ISA design is a balancing act Hardware complexity
Compiler complexity Programmer friendliness Backwards compatibility
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Choice 0 : Instruction Length
Will instructions be Fixed length ARM Easier to decode Variable length Intel Better use of space
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Choice 1 : Memory Model Memory Model
Is the machine little endian or big endian?
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Choice 1 : Memory Model Memory Model "Compute"
Is the machine little endian or big endian? "Compute" Which is easier for programmers to read? Big Endian +0 +1 +2 +3 0000 C o m p 0004 u t e \0 Little Endian +3 +2 +1 +0 0000 p m o C 0004 \0 e t u
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Choice 1 : Memory Model Memory Model
Is the machine little endian or big endian? -16 (FFFFFFF0) followed by 5 ( ) Which is easier to convert int to char? Big Endian +0 +1 +2 +3 0000 FF F0 0004 00 05 Little Endian +3 +2 +1 +0 0000 FF F0 0004 00 05
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Who uses what? ARM was little endian up to v3
Now can be used little or big
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Choice 2 : CPU Storage How will CPU store data?
General Purpose vs Special Purpose Registers How many?
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Choice 2 : CPU Storage Accumulator architecture Single Result Register
Shorter instructions Add X vs Add $9, $8, $7 More fiddly to program
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Choice 2 : CPU Storage General Purpose Registers
Any data (mostly) anywere ARM style More flexible/easier to program
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Choice 2 : CPU Storage Special Purpose Registers
Intel: Some instructions must work with specific registers Motorola: Separate data/address registers
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Choice 2 : CPU Storage How many? Fewer = more data shuffling More =
More hardware More bits eaten up in instructions 8 registers = 3 bits 16 registers = 4 bits 32 regisers = 5 bits
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Choice 3 : Addressing Modes
How restricted are we to registers? Memory-Memory Can work directly with memory in all instructions Memory Address are BIG!!! Register-Memory (Intel) At least one operand in register, other can be directly from memory Load-Store (ARM) Only special load/store instructions can reference memory More Flexible More Complex
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Choice 3 : Addressing Modes
How can we address memory: Directly MOV eax, [0x1040] Indirectly LDR r0, [r1] 0x1040
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Choice 4 : What Operations
Lots of different instructions/formats? CISC More hardware Shorter programs Longer opcodes Fewer machine instructions RISC 500 instructions * 4 addressing modes = 2000 instructions = 11 bit opcodes 100 instructions * 2 addressing modes = 200 instructions = 8 bit opcodes
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Choice 3 : Number of Operands
How many operands? 0 : ADD Stack based operations 1 : ADD 100 LMC 2 : Add r2, r3 Intel 3 : Add r2, r3, r4 Longer, More flexible Instructions
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Examples 3 Operand Instructions: Z = X Y + W U R1 X R2 Y R3 W R4 U
LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R1,R2 MULT R3,R3,R4 ADD R1,R1,R3 STORE Z, R1 R1 X R2 Y R3 W R4 U
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Examples 3 Operand Instructions: Z = X Y + W U R1 XY R2 Y R3 W R4
LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R1,R2 MULT R3,R3,R4 ADD R1,R1,R3 STORE Z, R1 R1 XY R2 Y R3 W R4 U
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Examples 3 Operand Instructions: Z = X Y + W U R1 XY R2 Y R3 WU R4
LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R1,R2 MULT R3,R3,R4 ADD R1,R1,R3 STORE Z, R1 R1 XY R2 Y R3 WU R4 U
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Examples 3 Operand Instructions: Z = X Y + W U R1 XY + WU R2 Y R3
LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R1,R2 MULT R3,R3,R4 ADD R1,R1,R3 STORE Z, R1 R1 XY + WU R2 Y R3 WU R4 U
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Examples 3 Operand Instructions: Z = X Y + W U R1 XY + WU R2 Y R3
LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R1,R2 MULT R3,R3,R4 ADD R1,R1,R3 STORE Z, R1 R1 XY + WU R2 Y R3 WU R4 U
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2 Operand 2 Operand Instructions
First operand is source and destination ADD r1, r2 r1 = r1 + r2 Intel style:
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Examples 2 Operand Instructions: Z = X Y + W U R1 X R2 Y R3 W R4 U
LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R2 MULT R3,R4 ADD R1,R3 STORE Z, R1 R1 X R2 Y R3 W R4 U
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Examples 2 Operand Instructions: Z = X Y + W U R1 XY R2 Y R3 W R4
LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R2 MULT R3,R4 ADD R1,R3 STORE Z, R1 Destination always same as first operand R1 XY R2 Y R3 W R4 U
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Examples 2 Operand Instructions: Z = X Y + W U R1 XY R2 Y R3 WU R4
LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R2 MULT R3,R4 ADD R1,R3 STORE Z, R1 R1 XY R2 Y R3 WU R4 U
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Examples 2 Operand Instructions: Z = X Y + W U R1 XY + WU R2 Y R3
LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R2 MULT R3,R4 ADD R1,R3 STORE Z, R1 R1 XY + WU R2 Y R3 WU R4 U
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Examples 2 Operand Instructions: Z = X Y + W U R1 XY + WU R2 Y R3
LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R2 MULT R3,R4 ADD R1,R3 STORE Z, R1 R1 XY + WU R2 Y R3 WU R4 U
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Examples 1 Operand Instructions - Accumulator Z = X Y + W U AC X
LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z AC X Destination assumed to be accumulator
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Examples 1 Operand Instructions - Accumulator Z = X Y + W U AC X*Y
LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z AC X*Y Destination assumed to be accumulator
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Examples 1 Operand Instructions - Accumulator Z = X Y + W U AC X*Y
LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z AC X*Y temp X*Y
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Examples 1 Operand Instructions - Accumulator Z = X Y + W U AC W
LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z AC W temp X*Y
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Examples 1 Operand Instructions - Accumulator Z = X Y + W U AC W*U
LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z AC W*U temp X*Y
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Examples 1 Operand Instructions - Accumulator Z = X Y + W U AC
LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z AC W*U + X*Y temp X*Y
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Examples 1 Operand Instructions - Accumulator Z = X Y + W U AC
LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z AC W*U + X*Y temp X*Y 7 trips to main memory!!!
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Stack Based Stack based CPU storage Loads place value on stack
Math operations pop top two values, work with them, push answer Store pops value off stack
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Choice 2 : CPU Storage Java bytecode is stack based language: Pro/Con
+ Instruction Size + Hardware neutrality - Does not take advantage of complex hardwar - Lots of memory access
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Examples 1 Operand Instructions – Stack based Z = X Y + W U X
PUSH X PUSH Y MULT PUSH W PUSH U ADD STORE Z X Destination assumed to be top of stack
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Examples 1 Operand Instructions – Stack based Z = X Y + W U Y X
PUSH X PUSH Y MULT PUSH W PUSH U ADD STORE Z Y X Destination assumed to be top of stack
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Examples 1 Operand Instructions – Stack based Z = X Y + W U X * Y
PUSH X PUSH Y MULT PUSH W PUSH U ADD STORE Z X * Y Take off top two items, multiply, put result back on stack
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Examples 1 Operand Instructions – Stack based Z = X Y + W U W
PUSH X PUSH Y MULT PUSH W PUSH U ADD STORE Z W X * Y
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Examples 1 Operand Instructions – Stack based Z = X Y + W U U W
PUSH X PUSH Y MULT PUSH W PUSH U ADD STORE Z U W X * Y
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Examples 1 Operand Instructions – Stack based Z = X Y + W U W * U
PUSH X PUSH Y MULT PUSH W PUSH U ADD STORE Z W * U X * Y Take off top two items, multiply, put result back on stack
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Examples 1 Operand Instructions – Stack based Z = X Y + W U PUSH X
PUSH Y MULT PUSH W PUSH U ADD STORE Z W * U + X * Y Take off top two items, add, put result back on stack
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Examples 1 Operand Instructions – Stack based Z = X Y + W U PUSH X
PUSH Y MULT PUSH W PUSH U ADD STORE Z 11-14 trips to main memory (Mult/Add 2 or 3 each!)
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