1. Computer Organization and Architecture + Networks
Lecture 4
Instruction Sets:
Characteristics and Functions
Addressing Modes and Formats

2. KEY POINTS
The essential elements of a computer instruction are the opcode, which specifies the operation to be performed; the source and destination operand references, which specify the input and output locations for the operation; and a next instruction reference, which is usually implicit.
Opcodes specify operations in one of the following general categories: arithmetic and logic operations; movement of data between two registers, register and memory, or two memory locations; I/O; and control.
Operand references specify a register or memory location of operand data. The type of data may be addresses, numbers, characters, or logical data.
A common architectural feature in processors is the use of a stack, which may or may not be visible to the programmer. Stacks are used to manage procedure calls

3. KEY POINTS
and returns and may be provided as an alternative form of addressing memory. The basic stack operations are PUSH, POP, and operations on the top one or two stack locations. Stacks typically are implemented to grow from higher addresses to lower addresses.
Processors may be categorized as big-endian, little-endian, or bi-endian. A multibyte numerical value stored with the most significant byte in the lowest numerical address is stored in big-endian fashion; if it is stored with the most significant byte in the highest numerical address, that is little-endian fashion. A bi-endian processor can handle both styles.

4. KEY POINTS
An operand reference in an instruction either contains the actual value of the operand (immediate) or a reference to the address of the operand. A wide variety of addressing modes is used in various instruction sets. These include direct (operand address is in address field), indirect (address field points to a location that contains the operand address), register, register indirect, and various forms of displacement, in which a register value is added to an address value to produce the operand address
The instruction format defines the layout fields in the instruction. Instruction format design is a complex undertaking, including such considerations as instruction length, fixed or variable length, number of bits assigned to opcode and each operand reference, and how addressing mode is determined.

5. Introduction
CPU: contains Registers, Control Unit, Interconnection and Arithmetic and Logic Unit (ALU)
ALU: comprises Arithmetic (discussed in previous note) + Logic Unit (this note)
Machine Instruction Sets: boundary for computer designer and computer programmer can seen the same machine
To computer designer: machine instruction sets – provides the functional requirements for the processor
To computer programmer: machine instruction sets – becomes aware of the register and memory structure and types of data supported by the machine 2

6. What is an Instruction Set?
Instruction Set is the complete collection of instructions that are understood by a CPU/processor
Each instruction must contain 4 elements of information for execution
Operation code
Source operand reference
Result reference
Next instruction reference 2

7. Instruction Set: 4 Elements
Operation code (Opcode)
specifies the operation to be performed (expressed as a binary code)  Do this
Source Operand reference
operands required for the instruction are specified  To this (memory/input-output/processor register)
Result Operand reference
where should the result of the operation to be placed? Put the answer here (memory/input-output/processor register)
Next Instruction Reference
how / where is the next instruction to be found  When you have done that, do this… 3

8. Simple Instruction Format
Each instruction is represented by a sequence of bits.
The instruction is divided into fields, corresponding to the constituent elements of the instruction.

9. Instruction Set: Representation & Types
Instruction Representation
Each instruction is represented by a sequence of bits
A symbolic representation is used eg. ADD, SUB, LOAD
Operands can also be represented in this way eg. ADD A,B (Add B to A and Store in A)
Instruction Types (4 Types of Instructions)
Data processing  Arithmetic and Logic Instructions
Data storage (main memory)  Memory Instructions
Data movement (I/O)  I/O Instructions
Program flow control  Test and Branch Instructions 4

10. Instruction Set: Number of Addresses
Number of Addresses in each instructions
3 addresses: Operand 1, Operand 2, Result
(2 Source Locations) (1 Destination)
a = b + c;
Not common because it needs very long words to hold the address
2 addresses: One address doubles as operand and result
a = a + b
Reduces length of instruction
1 address: Implicit (Internal) second address
Usually a register (accumulator); Acc = Acc + a
Common on early machines 4

11. Instruction Set 0 (zero) addresses: All addresses implicit (Internal)
Uses a stack (Special Memory Organization; Use the top 2 elements in Processor Registers)
Push: include a new element on top of the stack
Pop: transfer the top element of the stack to destination
Eg. c = a + b (push a; push b; add ; pop c;)
Consider: Y = (A-B) / (C+D*E)
3 addresses  2 addresses
SUB Y,A,B YA-B MOV Y,A YA
MUL T,D,E TDxE SUB Y,B YY-B
ADD T,T,C TT+C MOV T,D TD
DIV Y,Y,T YY/T MUL T,E TTxE
ADD T,C TT+C
DIV Y,T YY/T 4

12. Instruction Set 1 address  0 address
LOAD D ACD >> Converts to postfix MUL E ACACxE (reverse Polish) notation:
ADD C ACAC+C Y = AB-CDE*+/
STORE Y YAC PUSH A
LOAD A ACA PUSH B
SUB B ACAC-B SUB
DIV Y ACAC/Y PUSH C
STORE Y YAC PUSH D
PUSH E
MUL
ADD
DIV
POP Y 4

13. How Many Addresses More addresses Fewer addresses
More complex instructions
More registers
Inter-register operations are quicker
Fewer instructions per program
Fewer addresses
Less complex instructions
More instructions per program
Faster fetch/execution of instructions 11

14. Instruction Set Design
The design of Instruction Set in complex
Programmer have control of the processor through Instruction Set
Issue of Instruction Set Design:
Operation repertoire
How many ops?
What can they do?
How complex are they?
Data types
Instruction formats
Length of op code field
Number of addresses 12

15. Instruction Set Design
Registers
Number of CPU registers available
Which operations can be performed on which registers?
Addressing modes (later…) 13

16. Machine Instruction operates on data Categories of data are:
Types of Operand
Machine Instruction operates on data
Categories of data are:
Addresses
Numbers
Integer/floating point
Decimal numbers – necessity to convert from decimal to binary on input and from binary to decimal on output
Characters
ASCII, IRA(International Reference Alphabet) etc.
Logical Data
Bits or flags (1 – true or 0 – false) 14

17. Uses Little-Endian Style:
Pentium Data Types
General data types with 8 bit Byte, 16 bit word, 32 bit double word, 64 bit quad word
Uses Little-Endian Style:
Least Significant Byte is stored in the lowest address
Other numeric data format:
Byte unsigned int, Word unsigned int, Double precision floating point 15

18. Pentium Floating Point Data Types
Pentium Numeric Data Format
*Signed integers are in twos complement representation 17

19. Pentium Floating Point Data Types
Pentium Numeric Data Format
*Signed integers are in twos complement representation
*FP: actually refers to a set of types that are used by the FP unit and operated on by FP instructions 17

20. PowerPC Data Types
General data is same as in Pentium - 8 (byte), 16 (halfword), 32 (word) and 64 (doubleword) length data types
Use both little-endian/big-endian style (Least Significant Byte is stored in the highest address)
Other numeric format:
Unsigned byte (logical or integer arithmetic operations), unsigned halfword (unsigned byte), signed halfword, unsigned word, signed word, unsigned doubleword, byte string (0 to 128 bytes in length)

21. Types of Operation
Typical categorization of operations for Instruction sets on all machines:
Data Transfer
Arithmetic
Logical
Conversion
I/O
System Control
Transfer of Control 18

22. Length of data to be transferred Mode of addressing
Data Transfer
Move, Push, Pop, Load
Specify instruction
Location of the source and destination operands – each location could be memory, register or top of the stack
Length of data to be transferred
Mode of addressing 19

23. Basic arithmetic operation  Add, Subtract, Multiply, Divide
Signed Integer (fix-point numbers)
Floating point
May include
Increment (a++)
Decrement (a--)
Negate (-a)
Execution of arithmetic instruction may involve data transfer operations (refer program execution – Lecture 3) 20

24. Bitwise operations – basic logical operations
Boolean Operations
2 types operations
Bitwise operations – basic logical operations
Shifting and Rotating Function – bits of a word are shifted left or right P Q
NOT P
P AND Q
P OR Q
P XOR Q
P=Q 1 21

25. Shifting and Rotating Function
Logical
Shifting and Rotating Function 21

26. Shifting and Rotating Function
Logical
Shifting and Rotating Function
Logical shifts are useful for isolating fields within a word – 0s are shifted into a word to displace unwanted information that is shifted off the other end 21

27. Logical shifts: useful for isolating fields within a word
Eg. To send 2 characters to an I/O device 1 character at a time. If each memory word is 16 bits in length and contains 2 characters, this means that, 1 character is 8 bits. To send the 2 characters in a word, for the 1st character:
Load the word into a register and AND with (character on the right is masked out)
Shift to the right 8 times and shifts the remaining character to the right half of the register. Perform I/O. The I/O module reads the lower-order bits from the data bus. 21

28. Logical For the 2nd character:
Load the word into a register and AND with (character on the left is masked out)
Perform I/O. 21

29. Shifting and Rotating Function
Logical
Shifting and Rotating Function
Arithmetic shifts:
The sign bit is replicated into the bit position to its right
Logical left shift is performed on all bits but the sign bit is retained 21

30. Logical Arithmetic shifts:
Treats the data as signed integer and does not shift the sign bit
This operation can speed up certain arithmetic operations
Because of potential for overflow (overflow produces a different results), only certain processor has this instruction eg. IBM S/390 21

31. Shifting and Rotating Function
Logical
Shifting and Rotating Function
Rotate/Cyclic shifts: 21

32. Rotate/Cyclic shifts:
Logical
Rotate/Cyclic shifts:
Preserve all the bits being operated on
One application of rotate/cyclic shift: to bring each bit successively into the leftmost bit (this can be identified by testing the sign of the data
Input
Operation
Result
Logical right shift (3 bits)
Logical left shift (3 bits)
Arithmetic right shift (3 bits)
Arithmetic left shift (3 bits)
Right rotate (3 bits)
Left rotate (3 bits) 21

33. Change the format or Operate on the format of data
Conversion
Change the format or Operate on the format of data
E.g. Converting from Decimal to Binary and also conversion from one 8-bit code to another 22

34. May be specific instructions
Input/Output
May be specific instructions
May be done using data movement instructions (memory mapped)
May be done by a separate controller (DMA) 23

35. Eg. Instruction is used to read/modify a storage protection key
Systems Control
These instructions are for the use of operating system and are executed only while the processor is in certain privileged state.
Eg. Instruction is used to read/modify a storage protection key 24

36. to allow decision making to be implemented
Transfer of Control
In normal program, the instruction are implemented in sequence that is 1 instruction after another. But, sometimes, transfer of control is necessary because:
to allow repetition of instruction (more than 1 time); loop can be used
to allow decision making to be implemented
to allow a big tasks to be separated into smaller tasks
Most common transfer of control found in instruction sets are (i) branch (ii) skip (iii) procedure call 25

37. (i) Branch Instructions 2 types of branch:
Transfer of Control
(i) Branch Instructions
2 types of branch:
Conditional Branch: branch is taken only if certain condition is met eg. Branch to x if result is zero
Unconditional Branch: branch is always taken 25

38. Branch Instruction Branch from location 203 to 211 when X - Y = 0
Branch from location 225 to 235 when R1 = R2
Instructions in locations 202 through 210 will be executed repeatedly until the X-Y=0

39. (ii) Skip Instructions
Transfer of Control
(ii) Skip Instructions
This instruction includes an implied (indirect) address and does not require a destination address field.
One instruction is to be skipped
Implied address = address of the next instruction + 1 instruction length
Eg. Increment and skip if zero (ISZ)
301 •
309 ISZ R1
310 Branch xxxx
311 25

40. (ii) Skip Instructions 301
Transfer of Control
(ii) Skip Instructions
301 •
309 ISZ R1
310 Branch xxxx
311
Register 1, R1, is set to a negative number equivalent to the number of iterations to be peformed. At the end of the loop, R1 is incremented and if is not = 0, program branch back to 301. Else (R1 = 0), program skips the branch and continues with the next instruction 25

41. (iii) Procedure Call Instructions
Transfer of Control
(iii) Procedure Call Instructions
Procedure: a self-working computer program that can be inserted into a larger program and can be called at any point 25

42. Nested Procedure Calls
Main Program starts at location 4000, which include a call to procedure PROC1
CPU suspends execution and begins execution of PROC1 by fetching the next instruction from location 4500
Within PROC1, there are two calls  PROC1 is suspended and PROC2 is executed
RETURN statement causes the CPU to go back to the calling program and continue execution

43. Instruction Sets: Addressing Modes
So far:
Focused on WHAT an instruction set does
 types of operands and operations, that may be specified by machine instructions
Now
Focused on HOW to specify the operands and operations of instructions
 How is the address of an operand specified  Addressing Modes
How are the bits of an instruction is organized to define the operand address and operation of that instruction  Instruction Formats

44. Addressing Modes
The requirement: to reference a large range of locations in main memory  Addressing Techniques
7 addressing modes/techniques: ①Immediate/②Direct/③Indirect/④Register/⑤Register Indirect/⑥Displacement/⑦Stack
All computer architectures  provides 1 or more than 1 of these addressing modes

45. Addressing Modes - Issues
How the processor know which addressing mode is being used
a. Looking at the opcodes (different opcodes for different addressing mode)
b. Looking at the mode field (mode field  1 or more bits in the Instruction Format
Effective Address (EA) Interpretation:
 System Without Virtual Memory: EA = Main Memory + Register
 System With Virtual Memory: EA = Virtual Address / Register
* Effective Address = actual address of the location containing the reference operand

46. ①Immediate Addressing
Operand is part of the instruction
Operand = address field
e.g. ADD 5
Add 5 to contents of accumulator
5 is operand
Used to define constants/set initial values of variables
No additional memory references are required after the fetch of the instruction
Size of the operand (mean its range of values)  limited range
Fast 3

47. ① Immediate Addressing Diagram
Instruction
Opcode
Operand
Twos complement form: the leftmost bit of the operand field as a sign bit 4

48. Effective address, EA = address field, A e.g. ADD A
②Direct Addressing
Address field of the instruction contains the affective address of the operand
Effective address, EA = address field, A
e.g. ADD A
Add contents of cell A to accumulator
Look in memory at address A for operand
Single memory reference (memory access) is required to fetch the operand
No additional calculations to work out effective address
Address range is limited by the address space (width of the field that contains the address reference) 5

49. ②Direct Addressing Diagram
Instruction
Opcode
Address A
Memory
A: Contents of an address field in the instruction
Operand 6

50. EA = (A) *( ) = contents of A
③Indirect Addressing
Memory cell pointed to by address field contains the address of (pointer to) the operand – specifies a memory location which contains the address of the data
EA = (A) *( ) = contents of A
Look in A, find address (A) and look there for operand
e.g. ADD (A)
Add contents of cell pointed to by contents of A to accumulator
2 memory accesses are required
Fetch effective address (EA) : 1st Access
Fetch the operand : 2nd Access 7

51. May be nested, multilevel, cascaded
③Indirect Addressing
Range of effective addresses = 2n where n = width of the memory data word
Number of locations that can be used hold the effective address = 2k where k = width of the instruction’s address field
May be nested, multilevel, cascaded
e.g. EA = (((A)))
Draw the diagram yourself
Multiple memory accesses to find operand
Hence slower 8

52. ③Indirect Addressing Diagram
Instruction
Opcode
Address A
Memory
Pointer to operand
Operand 9

53. Same as direct addressing but
④Register Addressing
Same as direct addressing but
Address field is held in specifies register location and not main memory address
EA = R
Only a small address field is needed in the instruction
Shorter instructions
Faster instruction fetch
Limited number of registers
No time consuming memory access are required
eg. of usage: storing of intermediate result in a calculation  save time 10

54. Very limited address space Multiple registers helps performance
④Register Addressing
Very limited address space
Multiple registers helps performance
Requires good assembly programming or compiler writing
N.B. C programming
register int a; 11

55. ④Register Addressing Diagram
Instruction
Opcode
Register Address R
Registers
Operand 12

56. ⑤Register Indirect Addressing
Same as indirect addressing but
Address field  specifies a register that contains the effective address
EA = (R)
Operand is in memory cell pointed to by contents of register R
Large address space (2n)
One fewer memory access than indirect addressing 13

57. Register Indirect Addressing Diagram
Instruction
Opcode
Register Address R
Memory
Registers
Pointer to Operand
Operand 14

58. ⑥Displacement Addressing
Combines direct addressing and register indirect addressing
EA = A + (R)
Address field hold two values in the instruction
A = Address Reference
R = Register Reference
or vice versa 15

59. Displacement Addressing Diagram
Instruction
Opcode
Register R
Address A
Memory
Registers
Pointer to Operand +
Operand 16

60. ⑥Displacement Addressing
3 common uses of displacement addressing
Relative Addressing
Base-Register Addressing
Indexing
A is added to the Program Counter (Register Reference) contents to cause a branch operation in fetching in the next instruction
EA = A + (PC) 15

61. ⑥Displacement Addressing
Base-Register Addressing
-A is a displacement added to the contents of the referenced “base register” to form EA
EA = A + (BR)
-used by programmers and O/S to identify the start of user areas/segment
Indexing
- Same as base addressing
- used within programs for accessing data structures eg. iterative operation
A, A+1, A+2, EA = A + (IR)
A, value stored in Instruction Address
R, indexed register; = 0; Register increment after every operation by 1 15

62. ⑥Displacement Addressing
*Indexing – Terms (1)
Autoindexing: automatically incrementing or decrementing the index register after each reference to it
EA = A + (R)
(R)  (R)  Autoindexing
Postindexing: Indexing is performed after the indirection
EA = (A) + (R)
The address field (A) is used to access a memory location containing a direct address. This address is then indexed by the register (R).
Useful for accessing 1 of a number of blocks of data 15

63. ⑥Displacement Addressing
*Indexing – Terms (2)
Preindexing: Indexing is performed before the indirection
EA = (A + (R))
Effective Address – contains the address of operand
Eg. of use: Multiway Branch Table
Set up a table of addresses starting at location A. By indexing into this table, the required location can be found 15

64. ⑦Stack Addressing
Stack: linear array of locations (aka Pushdown List/Last-in-First-Out (LIFO) Queue)
Associated with a stack  pointer whose value = address of the top of the stack and pointer is maintained in a register (register indirect addressing)
Machine instructions need not include a memory reference but implicitly (known/internally) operate on the top of the stack (operand = Top of the Stack)
e.g.
ADD Pop top two items from stack and add 21

65. ⑦Stack Addressing Diagram
Instruction
Opcode
Registers
Implicit
Top of Stack 12

66. Reverse Polish (Postfix) Conversion from infix to postfix Rules
⑦Stack Addressing
Reverse Polish (Postfix)
Conversion from infix to postfix Rules
Perform all arithmetic Inside Inner Parentheses
Inside Outer Prentheses
Multiplication/Division
Addition/Subtraction
e.g. (A + B) ＊ [C ＊ (D + E) + F]
① AB + DE + 　　②　C ＊ F + ③ ＊
 AB + DE + C ＊ F + ＊
e.g. Infix Postfix
A+B  AB+
A+(B×C)  BC×A+ or ABC×+ 21

67. Reverse Polish (Postfix)
e.g. Infix Postfix
(A+B) ×C  AB+C×
A×B +C  AB×C+
A×B+C×D  AB×CD×+
A×B/C  AB×C/
((A+B) ×C+D)/(E+F+G) 
AB+C×D+EF+G+/
e.g. (3＊4)+(5＊6)  34＊56＊+
Stack Operation  21

68. Reverse Polish (Postfix)
Stack Operation  3 4 12 6 5 30 42
Push
Mul
Add
Pop ＊ ＋ 21

69. Numerical Eg. For Addressing Modes
*Obj. of addressing: Represent operand in memory/register
Contents of Processor, Register
Contents of Index Register
(Instruction Address)
(Receives Operand After Execution of Instruction
PC=200
R1=400
IR=400 AC
Address
Memory
201
202
400
399
500
600
702
800
200
Load to AC
Mode
Address = 500
Next Instruction
450
700
800
900
325
300
Addressing Effective Content
Mode Address of AC
Direct (EA=A)
Immediate (Op=A)
Indirect (EA=(A))
Register (EA=R) (No register, R1 location provided R1 contains operand)
Register (EA=(R))
Indirect
Relative (EA=A+(PC)) ( =702); PC after fetch and during execute=202
Indexed (EA=A+(IR) (EA=(IR)+500= =600) 21

70. Pentium Addressing Modes
Pentium address translation mechanism produces virtual or effective address is offset into segment
Starting address of the segment plus offset (effective address) gives linear address (Physical Address in memory)
This goes through page translation if paging enabled
12 addressing modes available
Immediate
Register operand
Displacement
Base
Base with displacement
Scaled index with displacement
Base with index and displacement
Base scaled index with displacement
Relative

71. Pentium Addressing Mode Calculation
Effective Address
Starting Address of the segment

72. PowerPC Addressing Modes
Load/store architecture
Indirect
Instruction includes 16 bit displacement to be added to base register (may be GP register) GP=General Purpose
Can replace base register content with new address
Indirect indexed
Instruction references base register and index register (both may be GP)
EA is sum of contents
Branch address
Absolute
Relative
Arithmetic
Integer Arithmetic: Operands in registers or part of instruction  use register and immediate addressing
Floating Point Arithmetic: all operands are in register only  use only register addressing

73. PowerPC Memory Operand Addressing Modes

74. Instruction Formats (IF)
Features of IF:
Defines the Layout of bits in an instruction
Must includes an opcode
Must includes (implicit or explicit) zero or more operand(s)
In most instruction sets, usually there are more than than one instruction format used
Basic IF design issues – includes Instruction Length, Allocation of Bits, Variable Length Instructions

75. Instruction Length Affected by and affects: Memory size
Memory organization
Bus structure
CPU complexity
CPU speed
Trade off between powerful instruction repertoire and saving space
Longer instruction lengths permit more opcodes, addressing modes, addressing ranges, etc.
Instruction lengths are equal to the basic memory transfer data size or a multiple of that size eg. If the memory system retrieves 32 bit words, instructions should be 32 bits (or 64)

76. Allocation of Bits Issue to allocate the bits in that format
Tradeoff between number of opcodes supported (rich instruction set) and the power of the addressing capability  (more opcodes, more bits in the opcode field and this reduces the bits available for addressing
Following are factors in determining the use of the addressing bits:
Number of addressing modes
Number of operands
Register versus memory
Number of register sets
Address range
Address granularity

77. PDP-8 Instruction Format
12-bit instruction length  supports approximately 35 instructions

78. PDP-10 Instruction Format
Stressed orthogonality (2 variables are independent of each other; in the context of instruction set, it means other element of an instruction set, it means other element of an instruction are independent of the opcode), completeness, and direct addressing
*completeness: arithmetic data have complete and identical set of operations
Tradeoff ease of programming with increased hardware expense (inefficient use of space)

79. Variable Length Instruction PDP-11 Instruction Format
Provide flexibility  more opcodes and memory addressing mode
Increases the complexity of the processor

80. VAX Instruction Examples
2 criteria in VAX instruction format:
All instructions have ‘neutral’ no of operands
All operands have same generality in specification
result in a highly variable instruction format
Operand Specifier = 1 Byte
Right-most 4-bits: Register
Comparison with VAX-Pentium & IBM S/370-Pentium
Pentium format-addressing mode is part of opcode sequence; VAX-addressing mode is part of operand
Pentium-allows 1-byte/2-byte & 4-byte offsets for indexing; IBM S/370-no greater than 4kB & offset must be positive

81. Pentium Instruction Format
Instruction: made up of
zero to 4 optional instruction prefixes
1/2-byte opcode
Optional address specifier (Mod R/m byte & Scale Index Byte
Optional displacement
Optional immediate field

82. PowerPC Instruction Formats (1)
Specify operation to be performed
32 bits long
Condition Register Conditional Branch Instruction
*Branching; eg: Branch if condition is true

83. PowerPC Instruction Formats (2)
3 source register  floating point arithmetic instructions

84. Foreground Reading
Stallings chapter 11
Intel and PowerPC Web sites