Download presentation
Presentation is loading. Please wait.
1
The fetch-execute cycle
2
Memory Address Register
+1 Program Counter Memory Memory Address Register Cell Selector Cells 69 70 Memory Data Register 71 72 Instruction Register Op Code Operand 73 Instruction Decoder ALU
3
Fetch +1 Program Counter 072 071 Memory Memory Address Register 071 69
Cell Selector Cells 69 70 Memory Data Register 251 71 251 72 Instruction Register 2 51 Op Code Operand 73 Instruction Decoder ALU
4
Decode +1 Program Counter Memory Memory Address Register 69 70
Cell Selector Cells 69 70 Memory Data Register 71 72 Instruction Register 2 51 Op Code Operand 73 Instruction Decoder ADD ALU
5
Execute +1 Program Counter Memory Memory Address Register 69 70
Cell Selector Cells 69 70 Memory Data Register 71 72 Instruction Register 2 51 Op Code Operand 73 Instruction Decoder ADD 51 ALU
6
Fetch +1 Program Counter 073 072 Memory Memory Address Register 072 69
Cell Selector Cells 69 70 Memory Data Register 226 71 72 Instruction Register 226 2 26 Op Code Operand 73 Instruction Decoder 51 ALU
7
Decode +1 Program Counter Memory Memory Address Register 69 70
Cell Selector Cells 69 70 Memory Data Register 71 72 Instruction Register 2 26 Op Code Operand 73 Instruction Decoder ADD 51 ALU
8
Execute +1 Program Counter Memory Memory Address Register 69 70
Cell Selector Cells 69 70 Memory Data Register 71 72 Instruction Register 2 26 Op Code Operand 73 Instruction Decoder 26 ADD 77 51 ALU
9
Exam question
Similar presentations
© 2025 SlidePlayer.com. Inc.
All rights reserved.