1. LOGIC FAMILIES
UNIT IV

2. ICs
Logic gates and memory devices are fabricated as IC s because components like resistors , diodes, BJTs ….. are an integral part of the chip
The various components are interconnected within the chip to form an e circuit during assembly
Advantages : increased reliability , reduced weight and size
SSI – fewer than 10 gates
MSI – gates/chip
LSI – gates/chip
VLSI – several 1000 gates
Ics – Digital /Analog

3. LOGIC FAMILIES Based on IC fabrication process – Bipolar and MOS
BIPOLAR: Elements – Resistors , Transistors and Diodes
Can be saturated or non saturated
SATURATED LOGIC: NON SATURATED LOGIC:
Resistor Transistor Logic Schottky Logic
Direct Coupled Transistor Logic Emitter – Coupled Logic
Diode Transistor Logic MOS FAMILIES
High Threshold Logic PMOS – P Channel MOSFET
Transistor - Transistor Logic NMOS – N Channel MOSFET
Integrated Injection Logic CMOS – Complementary MOS

4. CHARACTERISTICS – DIGITAL ICS
Speed of Operation/Propagation Delay:
The time taken for the output of the gate to change after the inputs have been changed
Power Dissipation:
Measure of power consumed by the logic gate when fully driven by all its inputs and is
expressed in mW/nW
Fan In:
No of inputs connected to the gate without any degradation in the voltage levels
4. Fan Out
Max no of similar logic gates that a gate can drive without any degradation in voltage levels
5. Noise Immunity:
Max noise voltage that may appear at the input of a logic gatewithout changing the logical state of its
output
The difference between the operating input logic voltage level and the threshold voltage – Noise Margin
Operating requirements -sensitive to temperature - varies between commercial, military , industrial applications
Power supply requirements

5. TRANSISTOR TRANSISTOR LOGIC -TTL
Fastest switching speed compared to others
Basic circuit – TTL logic family – NAND gate
Uses a special single multi emitter transistor that is fabricated with several emitters at its input– instead of diode – small area –yield increases- lower capacitance to the substrate – reduces circuit rise and fall time – high speed
No of emitters depends on fan in
Speed

6. TRANSISTOR TRANSISTOR LOGIC -TTL

7. TRANSISTOR TRANSISTOR LOGIC -TTL
Output from collector of transistor Q4
Each emitter of Q1 acts as diode
Q1 + 4 kohm - 3 input and gate-rest of the circuit acts like inverter
Overall circuit – 3 input nand gate
When a/b/c – are at 0 v (logic 0 ) –the corresponding EB junction Q1 F/W biased
Rb selected such that Q1 is turned on
Ib2 to base Q2 reduced potential of base of Q2
Q2 and Q4 -cut off
Output voltage Vcc - Logic 1

8. TRANSISTOR TRANSISTOR LOGIC -TTL
If all the inputs are high – logic 1 – EB of Q1 R/B Biased - No base current
Q1 off – CB F/W biased supplying Ib2 to Q2- Saturates Q2-Q2 on –Drop across R2 F/W biases BE juction of Q4-Q4 on
Output of the collector is low – Logic 0
The function of D – Prevents Q3 and Q4 simultaneously on
In the absence of diode Q3 conducts slightly- Output low
To prevent D between Q3 E and Q4 C
Volt drop across diode keeps BE jn of Q3 RB
Q4 conducts when output is low- NAND operation

9. TTL Gate with Totem-Pole Output(NAND)

10. EMITTER COUPLED LOGIC -ECL

11. EMITTER COUPLED LOGIC -ECL
Current mode logic
Non saturated digital logic family
Operates the transistors in active mode-Eliminates turn off/saturation delay – Faster switching speed among all bipolar devices
Propagation delay – 1 ns
Large Silicon area- Dissipates high power
Basic circuit – Differential amplifier
VEE – Fixed current IE
Depending upon Vin (Logic V or Logic V) Current switches between collectors of Q1 and Q2
Vc1 and Vc2 complements each other- Output voltage not equal to input logic levels
Made equal by emitter follower stages Q3 and Q4

12. ECL – NOR/OR GATE Basic ECL – Inverter – Output at Vout1
By connecting transistors in parallel with Q1 , the basic circuit can be expanded to more than one input
A, B Input s low – Q and Q1 both off – Q2 on – active region – Output collector at low state – A+B – collector of Q3 – A+B “
A or B high – Q or Q1 on - Q2 off – collector at high state – A+B – Collector of Q3 – A +B Complement

13. ECL NOR/OR GATE

14. CMOS FAMILIES
MOS – MOS structure – Metal electrode on an oxide insulator over a semi conductor substrate
PMOS – P channel enhancement MOSFET NMOS – N channel enhancement MOSFET CMOS – Both p and n channel devices

15. CMOS FAMILIES A B Y 1 P Channel MOS N Channel MOS Q1/Q2 Q3/Q4 ON OFF1 ON
OFF Q1 Q3 Q2 Q4
P Channel MOS
N Channel MOS

16. CMOS NOR GATE Q1 and Q2 – PMOS transistors
Q3 and Q4 – NMOS transistors
A and B low – Both PMOS ON – Both NMOS OFF Output – Vdd – HIGH
A or B high – associated PMOS OFF – associated NMOS ON – Output Low
CMOS OR – CMOS NOR+CMOS inverter

17. CMOS FAMILIES A B Y
Q1/Q4
Q3/Q2 1 ON
OFF Q1 Q3 Q4 Q2

18. CMOS NAND GATE Q1 and Q4 – PMOS transistors in parallel
Q2 and Q3 – NMOS transistors in series
A and B high – Both PMOS OFF – Both NMOS ON Output – Vdd – low
A or B low – associated PMOS On – associated NMOS Off – Output High
CMOS AND – CMOS NAND +CMOS inverter

19. CMOS INVERTER Q2 – driver , Q2 OFF –NMOS – Q1 – load , PMOS –
Drains connected together – Output
Source and substrate connected together
Gates to common input
Source of Q1 – VDD
Source of Q2 grounded
Vin low – Q2 OFF –Q1 ON - Output high
Vin High – Vice Versa - INVERTER

20. CMOS INVERTER

21. CPLD
PAL and GAL are available only in small sizes, equivalent to a few hundred logic gates. For bigger logic circuits, complex PLD (CPLD) can be used. These contain the equivalent of several PAL linked by programmable interconnections, all in one integrated circuit. CPLDs can replace thousands, or even hundreds of thousands, of logic gates.
FPGA
FPGA uses a grid of logic gates, similar to that of an ordinary gate array, but the programming of connection is done by the customer, not by the manufacturer.

22. FPGA Field Programmable Gate Array
Monolithic highly integrated circuits –VLSI
Custom- SEMI CUSTOM – Programmable logic
IC designed to be configured by a customer or a designer after manufacturing
Modern day technology for building a breadboard or prototype from standard parts
Programmable logic blocks and programmable interconnects allow the same FPGA to be used in many different applications
FPGA contain an array of programmable logic blocks and a hierarchy of reconfigurable interconnects that allows the blocks to be wired together like many logic gates that can be inter wired in different configurations
FPGA configuration is generally specified using a HARDWARE DESCRIPTION LANGUAGE (HDL) similar to Application Specific Integrated Circuit (ASIC)rate
9/20/2018

23. FPGA
Logic Blocks configured to perform combinational function. In most FPGAs logic blocks also include memory elements(FF) or complete blocks of memory
CLB – Configurable Logic Blocks –fundamental building block of FPGA technology
Contemporary FPGAs have large resources of logic gates and RAM blocks to implement complex digital computations.
9/20/2018

24. FPGA
FPGA s member of class of devices called FPL, defined as programmable devices containing repeated fields of small logic blocks and elements(Configurable Logic Blocks(CLB) by Xilinx & Logic cell/Logic element LC/LE by Altera)
Gate arrays typically consist of a sea of NAND gates whose functions are customer provided in a wire list
Wire list is used during the fabrication process to achieve the distinct definition of the final metal layer
The designer of a programmable gate array solution has full control over the actual design implementation without the need and delay for any physical IC fabrication facility
9/20/2018

25. FPGA - ARCHITECTURE LOGIC BLOCKS Programmable Interconnect
Routing channels
Programmable Peripheral Devices

26. FPGA (Field Programmable Gate Array)