1. Computer Architecture (CS 207 D) Instruction Set Architecture ISA

2. Instructions: Overview
Instructions is the language of the machine
More primitive than higher level languages, e.g., no sophisticated control flow such as while or for loops
Different computers have different instruction sets
Very restrictive e.g., MIPS arithmetic instructions
Large share of embedded core market, MIPS ISA typical of many modern ISAs
inspired most architectures developed since the 80's
used by NEC, Nintendo, Silicon Graphics, Sony
the name is not related to millions of instructions per second !
MIPS ISA stands for Microcomputer without Interlocked Pipeline Stages
Design goals: maximize performance and minimize cost and reduce design time

3. MIPS Arithmetic All MIPS arithmetic instructions have 3 operands
Two sources and one destination
Operand order is fixed (e.g., destination first)
Example: C code: A = B + C MIPS code: add $s0, $s1, $s2
All arithmetic operations have this form
compiler’s job to associate
variables with registers

4. MIPS Arithmetic Design Principle 1: simplicity favors regularity.
Translation: Regular instructions make for simple hardware!
Simpler hardware reduces design time and manufacturing cost.
Of course this complicates some things... C code: A = B + C + D; E = F - A; MIPS code add $t0, $s1, $s2 (arithmetic): add $s0, $t0, $s3 sub $s4, $s5, $s0
Performance penalty: high-level code translates to denser machine code.
Allowing variable number
of operands would
simplify the assembly
code but complicate the
hardware.

5. MIPS Arithmetic F=(g+h) - (i+j) add $t1, $s3, $s4 sub $s0, $t0, $t1
Operands must be in registers – only 32 registers provided (which require 5 bits to select one register). Reason for small number of registers:
Design Principle 2: smaller is faster. Why?
Electronic signals have to travel further on a physically larger chip increasing clock cycle time.
Smaller is also cheaper!
Example: C code
F=(g+h) - (i+j)
Compiled MIPS code
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1

6. Registers vs. Memory
Arithmetic instructions operands must be in registers
MIPS has 32 X 32 bit register file used for frequently accessed data
Compiler associates variables with registers numbered 0 to 31
Register names $t0, $t1, ….. $t9 for temporary values
Register names $S0, $S1, ….. $S7 for temporary values
What about programs with lots of variables (arrays, etc.)? Use memory, load/store operations to transfer data from memory to register – if not enough registers spill registers to memory
MIPS is a load/store architecture

7. Memory Organization
Viewed as a large single-dimension array with access by address
A memory address is an index of the memory array
Byte addressing means that the index points to a byte of memory, and that the unit of memory accessed by a load/store is a byte
8 bits of data
Processor
I/O
Control
Datapath
Memory
Input
Output 1
8 bits of data 2
8 bits of data 3
8 bits of data 4
8 bits of data 5
8 bits of data 6
8 bits of data
...

8. Memory Organization
Bytes are load/store units, but most data items use larger words
For MIPS, a word is 32 bits or 4 bytes.
232 bytes with byte addresses from 0 to 232-1
230 words with byte addresses 0, 4, 8,
i.e., words are aligned
what are the least 2 significant bits of a word address?
32 bits of data 4
Registers correspondingly hold 32 bits of data
32 bits of data 8
32 bits of data 12
32 bits of data
...

9. Load/Store Instructions
Load and store instructions
Example: C code: A[8] = h + A[8];
MIPS code (load): lw $t0, 32($s3) (arithmetic): add $t0, $s2, $t (store): sw $t0, 32($s3)
Load word has destination first, store has destination last
Remember MIPS arithmetic operands are registers, not memory locations
therefore, words must first be moved from memory to registers using loads before they can be operated on; then result can be stored back to memory
value
offset
address

10. So far we’ve learned: loading words but addressing bytes
MIPS
loading words but addressing bytes
arithmetic on registers only
Instruction Meaning add $s1, $s2, $s3 $s1 = $s2 + $s3 sub $s1, $s2, $s3 $s1 = $s2 – $s3 lw $s1, 100($s2) $s1 = Memory[$s2+100] sw $s1, 100($s2) Memory[$s2+100]= $s1

11. R-type Instruction
Instructions, like registers and words of data, are also 32 bits long
Example: add $t0, $s1, $s2
registers are numbered, e.g., $t0 is 8, $s1 is 17, $s2 is 18
Instruction Format R-type (“R” for aRithmetic):
000000
10001
10010
01000
00000
100000
6 bits bits bits bits bits bits
op rs rt rd shamt funct
opcode –
operation
first
register
source
operand
second
register
source
operand
register
destin-
ation
operand
shift
amount
function field -
selects variant
of operation

12. I- Type Instruction
Design Principle 3: Good design demands a compromise
Introduce a new type of instruction format
I-type (“I” for Immediate) for data transfer instructions
Example: lw $t0, 1002($s2)
op rs rt bit offset
6 bits bits bits bits

13. Memory Organization: Big/Little Endian Byte Order
Bytes in a word can be numbered in two ways:
byte 0 at the leftmost (most significant) to byte 3 at the rightmost (least significant), called big-endian
byte 3 at the leftmost (most significant) to byte 0 at the rightmost (least significant), called little-endian
MIPS is Big Ending
Big-endian
Memory
Little-endian
Memory
Bit 31
Bit 31
Bit 0
Bit 0
Byte 0
Byte 1
Byte 2
Byte 3
Word 0
Byte 3
Byte 2
Byte 1
Byte 0
Word 0
Byte 4
Byte 5
Byte 6
Byte 7
Word 1
Byte 7
Byte 6
Byte 5
Byte 4
Word 1

14. Control: Conditional Branch
Decision making instructions
alter the control flow,
i.e., change the next instruction to be executed
MIPS conditional branch instructions: bne $t0, $t1, Label beq $t0, $t1, Label
Example: if (i==j) h = i + j; bne $s0, $s1, Label add $s3, $s0, $s1 Label: ....
I-type instructions
beq $t0, $t1, Label
(= addr.100)
word-relative addressing:
25 words = 100 bytes;
also PC-relative (more…)

15. Addresses in Branch Instructions: Format:
bne $t4,$t5,Label Next instruction is at Label if $t4 != $t5
beq $t4,$t5,Label Next instruction is at Label if $t4 = $t5
Format:
16 bits is too small a reach in a 232 address space
Solution: specify a register (as for lw and sw) and add it to offset
use PC (= program counter), called PC-relative addressing, based on
principle of locality: most branches are to instructions near current instruction (e.g., loops and if statements) I
op rs rt bit offset

16. Addresses in Branch
Further extend reach of branch by observing all MIPS instructions are a word (= 4 bytes), therefore word-relative addressing:
MIPS branch destination address = (PC + 4) + (4 * offset)
so offset = (branch destination address – PC – 4)/4
but SPIM does offset = (branch destination address – PC)/4
Because hardware typically increments PC early
in execute cycle to point to next instruction

17. Control: Unconditional Branch (Jump)
MIPS unconditional branch instructions:
j Label
Example: if (i!=j) beq $s4, $s5, Lab h=i+j; add $s3, $s4, $s5 else j Lab h=i-j; Lab1: sub $s3, $s4, $s5 Lab2: ...
J-type (“J” for Jump) instruction format
Example: j Label # addr. Label = 100
word-relative
addressing:
25 words = 100 bytes
000010
6 bits bits op
26 bit number

18. Addresses in Jump Word-relative addressing also for jump instructions
MIPS jump j instruction replaces lower 28 bits of the PC with A00 where A is the 26 bit address; it never changes upper 4 bits
Example: if PC = 1011X (where X = 28 bits), it is replaced with 1011A00
there are 16(=24) partitions of the 232 size address space, each partition of size 256 MB (=228), such that, in each partition the upper 4 bits of the address is same.
if a program crosses an address partition, then a j that reaches a different partition has to be replaced by jr with a full 32-bit address first loaded into the jump register
therefore, OS should always try to load a program inside a single partition J
op bit address

19. Constants
Small constants are used quite frequently (50% of operands) e.g., A = A + 5; B = B + 1; C = C - 18;
Solutions? Will these work?
create hard-wired registers (like $zero) for constants like 1
put program constants in memory and load them as required
MIPS Instructions: addi $29, $29, 4 slti $8, $18, 10 andi $29, $29, 6 ori $29, $29, 4
How to make this work?

20. Immediate Operands Make operand part of instruction itself!
Design Principle 4: Make the common case fast
Example: addi $sp, $sp, 4 # $sp = $sp + 4
001000
11101
11101
6 bits bits bits bits op rs rt
16 bit number

21. In Summary
Instruction Format Meaning add $s1,$s2,$s3 R $s1 = $s2 + $s3 sub $s1,$s2,$s3 R $s1 = $s2 – $s3 lw $s1,100($s2) I $s1 = Memory[$s2+100] sw $s1,100($s2) I Memory[$s2+100] = $s1 bne $s4,$s5,Lab1 I Next instr. is at Lab1 if $s4 != $s5 beq $s4,$s5,Lab2 I Next instr. is at Lab2 if $s4 = $s5 j Lab3 J Next instr. is at Lab3
Formats: R I J
op rs rt rd shamt funct
op rs rt 16 bit address
op bit address

22. Control Flow Board work: Binary Numbers
We have: beq, bne. What about branch-if-less-than?
New instruction: if $s1 < $s2 then $t0 = 1 slt $t0, $s1, $s2 else $t0 = 0
Can use this instruction to build blt $s1, $s2, Label
how? We generate more than one instruction – pseudo-instruction
can now build general control structures
The assembler needs a register to manufacture instructions from pseudo-instructions
There is a convention (not mandatory) for use of registers
Board work: Binary Numbers

23. Policy-of-Use Convention for Registers
Register 1, called $at, is reserved for the assembler; registers 26-27,
called $k0 and $k1 are reserved for the operating system.

24. Assembly Language vs. Machine Language
Assembly provides convenient symbolic representation
much easier than writing down numbers
regular rules: e.g., destination first
Machine language is the underlying reality
e.g., destination is no longer first
Assembly can provide pseudo-instructions
e.g., move $t0, $t1 exists only in assembly
would be implemented using add $t0, $t1, $zero
When considering performance you should count actual number of machine instructions that will execute

25. MIPS Addressing Modes

26. Overview of MIPS Rely on compiler to achieve performance
Simple instructions – all 32 bits wide
Very structured – no unnecessary baggage
Only three instruction formats
Rely on compiler to achieve performance
what are the compiler's goals?
Help compiler where we can
op rs rt rd shamt funct R I
op rs rt 16 bit address
op bit address J

27. Summarize MIPS:

29. Translation from High Level Language to MIPS; Machine Language
C program

31. Summary Instruction set architecture
a very important abstraction indeed!
Design Principles:
simplicity favors regularity
smaller is faster
good design demands compromise
make the common case fast
Good design demands good compromises
Layers of software/ hardware
Compiler; assembler; hardware
MIPS is typical of RISC ISAs