1. CSE 140 MT 2 Review
By Daniel Knapp

2. Overview Sequential Networks Standard Combinational Modules
Introduction and memory components
Specification, analysis, and implementation
Timing
Standard Combinational Modules
Decoders and Encoders
Multiplexers (Mux) and Demultiplexers (Demux)
System Design (not heavy focus of MT 2)

3. Sequential Networks Latches (Level Sensitive)
SR Latches, D Latches
Flip-Flops (Edge Triggered)
D FFs, JK FFs, T FFs
Examples of Memory Modules
Registers, Shift Registers, Pattern Recognizers, Counters, FIFOs

4. Latches
Basic SR Latch

5. Latches cont.
D Latch (avoids SR 11 input)

6. Flip-Flops D Flip-Flop (all FFs are edge triggered)
State changes every rising edge of the CLK (NS becomes PS)

7. Flip-Flops cont.
JK Flip-Flop (edge triggered)

8. Flip-Flops cont.
T Flip-Flop (edge triggered)

9. Flip-Flops cont.

10. Finite State Machines Used to describe circuit behavior over time
Mealy- current state and current input; Moore- only current state

11. Finite State Machines cont.
Mealy Machine
Moore Machine

12. Finite State Machines cont.
Output of mealy machine is put on the transition, “1/0”
Output of moore machine belongs only to the state, not its transitions
Mealy Machine
Moore Machine

13. Finite State Machines cont.
Be able to draw this table for a state diagram
Mealy Machine
Moore Machine

14. Mealy to Moore Conversion

15. Mealy to Moore Conversion cont.1

16. Implementation Implementing JK FF with T FF
Inputs are J(t), K(t), and Q(t)
T(t) is the output of some combinational logic used as input to the T FF to change Q(t) to Q(t+1)
Q(t) is also the current output of the design
Q(t+1) is the next state

17. Implementation cont.
Good chance you may have something like HW4 prob 5 on the midterm
Be able to
Create state diagram from a given description
Write a state table
Write an excitation table which includes specific FF inputs if the problem asks to design using some specific type of Flip-Flops
Draw K-maps derived from the excitation table
Create a minimum SOP or POS expression for each K-map
Draw the logic diagram for the system

18. Implementation cont.
Good chance you may have something like HW4 prob 5 on the midterm
Be able to
Create state diagram from a given description
Write a state table
Write an excitation table which includes specific FF inputs if the problem asks to design using some specific type of Flip-Flops
Draw K-maps derived from the excitation table
Create a minimum SOP or POS expression for each K-map
Draw the logic diagram for the system

19. Timing

20. Timing cont.

21. Timing cont.

22. Timing cont.

23. Timing cont.

24. Timing cont. Add in skew… This formula is worst case for setup time
May be able to decrease clock period if skew is best case (retiming)
Worst Case
Best Case

25. Timing cont.
Add in skew…

26. Timing cont.
When retiming, find max skew tolerable with hold time equation
Then plug the skew into the best case scenario for the setup time equation to get an improved clock period

27. Standard Combinational Modules
Commonly used combinational circuits that are more complicated than gates
Many of them are used to implement control logic for system design

28. Decoder

29. Encoder

30. Priority Encoder

31. Multiplexer

32. Demultiplexer

33. System Design
Focus on understanding the other topics thoroughly and if you have more time, review the system design podcast
Better to handle questions from this material on piazza or office hours than at the review session today since the other material would cover the bulk of the points