1. Shift Registers

2. Topics Introduction Buffer Register Classification of Register
Shift Registers and their modes
Bidirectional Shift Register
Universal Shift Register

3. Introduction Register is an important application of Flip-Flop.
Flip- Flop is a 1 bit memory cell which can be used for storing the digital data.
To increase the storage capacity in terms of number of bits, we have to use a group of flip-flop. Such a groups of flip-flop is known as a “Register”.
Thus register is a group of flip-flops. The “n-bit” register will consist of “n” number of flip flops.

4. Buffer Register Constructed by using D flip-flop.
We can use any type of edge triggering. But here it is a positive triggered D flip-flop.
Operation
The data is to be stored is B3B2B1B0 =
These bits are connected to each D-Flip-flops.
Then the clock is applied and corresponding output will be
Q3Q2Q1Q0 = B3B2B1B0 =

5. Buffer Register 4 bits input B3 B2 B1 B0 Q3 D3 Q2 D2 Q1 D1 Q0 D0 FF-3
CLK Q3 Q2 Q1 Q0
Outputs

6. Operation of Buffer Register
4 bits input B3 B2 B1 B0 1 1 Q3 D3 Q2 D2 Q1 D1 Q0 D0
FF-3
FF-2
FF-1
FF-0
CLK 1 1 Q3 Q2 Q1 Q0
Outputs

7. Classification of Registers :
Mode of operation
Serial in serial out
(SISO)
Shift Right
Shift Left
Serial in Parallel out
(SIPO)
Parallel in Serial out
(PISO)
Parallel in Parallel out
(PIPO)

8. Shift Register Comments Mode Illustrative Diagram 1.
Sr. No.
Mode
Illustrative Diagram
Comments 1.
SISO (Shift Right)
Data bits shift from Left to Right by 1 position per clock cycle. 2.
SISO (Shift Left)
Data bits shift from Right to Left by 1 position per clock cycle. 3.
SIPO
All o/p bits are made aval. simult. after clcok pulse 4.
PISO
All i/p bits are applied simult and. After 4-clk pulse the required o/p is available serially.
I/P
FF3
FF2
FF1
FF0
O/P
FF3
FF2
FF1
FF0
O/P
I/P
FF3
FF2
FF1
FF0
I/P
O/P
I/P
FF3
FF2
FF1
FF0
O/P

9. Serial input Serial Output (Shift Left Mode)
Din Q3 D3 Q2 D2 Q1 D1 Q0 D0
FF-3
FF-2
FF-1
FF-0
Serial
Data
Output
CLK
Serial Shift left register
Before application of clock let assume all outputs are zero and apply MSB bit of the number to entered to Din. So Din = D0 = 1.

10. Serial input Serial Output (Shift Left Mode)
Apply the clock . On the first falling edge of clock, the FF-0 is SET and the stored data in the register is
Q3Q2Q1Q0 =
Din 1 1 Q3 D3 Q2 D2 Q1 D1 Q0 D0
FF-3
FF-2
FF-1
FF-0
CLK
Serial
Data
Output

11. Serial input Serial Output (Shift Left Mode)
Apply the NEXT bit to Din . So if Din =1.
As soon as the next positive edge of the clock hits. FF- 1 will SET and the stored data changes to,
Q3Q2Q1Q0 =
Din 1 1 1 Q3 D3 Q2 D2 Q1 D1 Q0 D0
FF-3
FF-2
FF-1
FF-0
CLK
Serial
Data
Output

12. Serial input Serial Output (Shift Left Mode)
Apply the NEXT bit to Din . So if Din =1.
As soon as the next positive edge of the clock hits. FF- 2will SET and the stored data changes to,
Q3Q2Q1Q0 =
Din 1 1 1 1 Q3 D3 Q2 D2 Q1 D1 Q0 D0
FF-3
FF-2
FF-1
FF-0
CLK
Serial
Data
Output

13. Serial input Serial Output (Shift Left Mode)
Apply the NEXT bit to Din . So if Din =1.
As soon as the next positive edge of the clock hits. FF- 3will SET and the stored data changes to,
Q3Q2Q1Q0 =
Din 1 1 1 1 1 Q3 D3 Q2 D2 Q1 D1 Q0 D0
FF-3
FF-2
FF-1
FF-0
CLK
Serial
Data
Output

14. Summary of shift left operation
CLK Q3
Q2=D3
Q1=D2
Q0=D1
Serial input Din = D0 1

15. Serial input Serial Output (Shift Right Mode)Q0
FF-0 D1 Q1
FF-1 D2 Q2
FF-2 D3 Q3
FF-3
Din
CLK
Serial
Output

16. Serial input Parallel Output (SIPO)
In this operation the data is entered serially and taken out in parallel.
That means first the data is loaded bit by bit. The output are disabled as the loading is taking place.
Number of clock cycles required to load a four bits data is 4. Hence the speed of operation of SIPO mode is same as that of SISO mode. D3 Q3
FF-3 D2 Q2
FF-2 D1 Q1
FF-1 D0 Q0
FF-0
Din
CLK

17. Parallel input Parallel Output (PIPO)
In this operation the data are entered parallel.
The 4-bit binary input B0, B1, B2, B3 is applied to data inputs D0, D1, D2 and D3 respectively of the four flip-flops.
As soon as a positive clock edge is applied, the input binary bits will be loaded into the flip-flops simultaneously.
The loaded bits will appear simultaneously to the output side. ONLY ONE CLOCK IS ESSENTIAL TO LOAD ALL THE BITS. B0 B1 B2 B3 D0 Q0 D1 Q1 D2 Q2 D3 Q3
FF-0
FF-1
FF-2
FF-3
CLK Q2 Q3 Q0 Q1

18. Parallel input Serial Output (PISO)
In this operation the data are entered parallel.
Output of pervious FF is connected to the input of the next via a combinational circuit.
The binary input data B0, B1, B2, B3 is applied through the same the combinational circuit.
There are two modes in which this circuit can work namely shift mode or load mode.

19. D3 Q3 FF-3 D2 Q2 FF-2 D1 Q1 FF-1 D0 Q0 FF-0 B0 CLK B1 B2 B3 6 5 4 3 2
Shift/ Load 6 5 4 3 2 1
Serial
Data O/P

20. 4-bits Bidirectional Shift Register

21. D0 Q0 FF-0 D1 Q1 FF-1 D2 Q2 FF-2 D3 Q3 FF-3 CLK 8 7 6 5 4 3 2 1
MODE BIT M 8 7 6 5 4 3 2 1
Serial
Shift Left
Input DL
Shift Right
Input DR
M=1 Shift Right
M=0 Shift Left

22. 4-bits Universal Shift Register
Mode Control
S S0
Register Operation
No change 1
Shift Right
Shift Left
Parallel load

24. Applications of shift Register
For Temporary data storage.
For multiplication and division
As a delay line
Ring Counter
Parallel to serial converter