1. Instructor: Alexander Stoytchev
CprE 281: Digital Logic
Instructor: Alexander Stoytchev

2. Counters & Solved Problems
CprE 281: Digital Logic
Iowa State University, Ames, IA
Copyright © 2013

3. Administrative Stuff
Homework 9 is out
It is due on Monday Nov 6

4. Counters

5. T Flip-Flop (circuit and graphical symbol)
[ Figure 5.15a,c from the textbook ]

6. The output of the T Flip-Flop divides the frequency of the clock by 2

7. The output of the T Flip-Flop divides the frequency of the clock by 21

8. A three-bit down-counter
[ Figure 5.20 from the textbook ]

9. A three-bit down-counter
The first flip-flop changes
on the positive edge of the clock
[ Figure 5.20 from the textbook ]

10. A three-bit down-counter
The first flip-flop changes
on the positive edge of the clock
The second flip-flop changes
on the positive edge of Q0
[ Figure 5.20 from the textbook ]

11. A three-bit down-counter
The first flip-flop changes
on the positive edge of the clock
The second flip-flop changes
on the positive edge of Q0
The third flip-flop changes
on the positive edge of Q1
[ Figure 5.20 from the textbook ]

12. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
[ Figure 5.20 from the textbook ]

13. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
least
significant
most

14. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
Q0 toggles
on the positive
clock edge

15. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
Q1 toggles
on the positive
edge of Q0

16. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
Q2 toggles
on the positive
edge of Q1

17. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
The propagation delays get longer

18. A three-bit up-counter
[ Figure 5.19 from the textbook ]

19. A three-bit up-counter
The first flip-flop changes
on the positive edge of the clock
[ Figure 5.19 from the textbook ]

20. A three-bit up-counter
The first flip-flop changes
on the positive edge of the clock
The second flip-flop changes
on the positive edge of Q0
[ Figure 5.19 from the textbook ]

21. A three-bit up-counter
The first flip-flop changes
on the positive edge of the clock
The second flip-flop changes
on the positive edge of Q0
The third flip-flop changes
on the positive edge of Q1
[ Figure 5.19 from the textbook ]

22. A three-bit up-counterQ
Clock 1 2
(a) Circuit
Count 3 4 5 6 7
(b) Timing diagram
[ Figure 5.19 from the textbook ]

23. A three-bit up-counter
[ Figure 5.19 from the textbook ] T Q
Clock 1 2
(a) Circuit
Count 3 4 5 6 7
(b) Timing diagram
least
significant
most

24. A three-bit up-counterQ
Clock 1 2
(a) Circuit
(b) Timing diagram
The count
is formed
by the Q’s
[ Figure 5.19 from the textbook ]

25. A three-bit up-counterQ
Clock 1 2
(a) Circuit
(b) Timing diagram
The toggling
is done
by the Q’s

26. A three-bit up-counterQ
Clock 1 2
(a) Circuit
(b) Timing diagram
Q0 toggles
on the positive
clock edge

27. A three-bit up-counterQ
Clock 1 2
(a) Circuit
(b) Timing diagram
Q1 toggles
on the positive
Edge of Q0

28. A three-bit up-counterQ
Clock 1 2
(a) Circuit
(b) Timing diagram
Q2 toggles
on the positive
edge of Q1

29. A three-bit up-counterQ
Clock 1 2
(a) Circuit
(b) Timing diagram
The propagation delays get longer

30. A three-bit up-counter1 T Q T Q T Q
Clock Q Q Q Q Q Q 1 2
The propagation delays get longer
(a) Circuit
Clock Q Q 1 Q 2
Count 1 2 3 4 5 6 7
(b) Timing diagram
[ Figure 5.19 from the textbook ]

31. Synchronous Counters

32. A four-bit synchronous up-counter
[ Figure 5.21 from the textbook ]

33. A four-bit synchronous up-counter
The propagation delay through all AND gates combined must
not exceed the clock period minus the setup time for the flip-flops
[ Figure 5.21 from the textbook ]

34. A four-bit synchronous up-counterQ
Clock 1 2
(a) Circuit
Count 3 5 9 12 14
(b) Timing diagram 4 6 8 7 10 11 13 15
[ Figure 5.21 from the textbook ]

35. Derivation of the synchronous up-counter1 2 3 4 5 6 7
Clock cycle 8 Q
changes
[ Table 5.1 from the textbook ]

36. Derivation of the synchronous up-counter1 2 3 4 5 6 7
Clock cycle 8 Q
changes
T0= 1
T1 = Q0
T2 = Q0 Q1
[ Table 5.1 from the textbook ]

37. A four-bit synchronous up-counter
T1 = Q0
T2 = Q0 Q1
[ Figure 5.21 from the textbook ]

38. In general we have T0= 1 T1 = Q0 T2 = Q0 Q1 T3 = Q0 Q1 Q2 …
Tn = Q0 Q1 Q2 …Qn-1

39. Synchronous v.s. Asynchronous Clear

40. 2-Bit Synchronous Up-Counter (without clear capability)1 T Q
Clock Q0 Q1

41. 2-Bit Synchronous Up-Counter (with asynchronous clear)1 T Q
Clock
Clear_n Q0 Q1

42. 2-Bit Synchronous Up-Counter (with asynchronous clear)1 D Q
Clock
Clear_n Q0 Q1
This is the same circuit but uses D Flip-Flops.

43. 2-Bit Synchronous Up-Counter (with synchronous clear)1 D Q
Clock
Clear_n Q0 Q1
This counter can be cleared only on the positive clock edge.

44. Adding Enable Capability

45. A four-bit synchronous up-counter
[ Figure 5.21 from the textbook ]

46. Inclusion of Enable and Clear CapabilityQ
Clock
Enable
Clear_n
[ Figure 5.22 from the textbook ]

47. Inclusion of Enable and Clear Capability
This is the new thing relative to
the previous figure, plus the clear_n line T Q
Clock
Enable
Clear_n
[ Figure 5.22 from the textbook ]

48. Providing an enable input for a D flip-flop
[ Figure 5.56 from the textbook ]

49. Synchronous Counter
(with D Flip-Flops)

50. A 4-bit up-counter with D flip-flops
[ Figure 5.23 from the textbook ]

51. A 4-bit up-counter with D flip-flops
T flip-flop
T flip-flop
T flip-flop
T flip-flop
[ Figure 5.23 from the textbook ]

52. Equivalent to this circuit with T flip-flops
Enable T Q T Q T Q T Q
Clock Q Q Q Q

53. Equivalent to this circuit with T flip-flopsZ
Enable T Q T Q T Q T Q
Clock Q Q Q Q
But has one extra output called Z, which can be used to
connect two 4-bit counters to make an 8-bit counter.
When Z=1 the counter will go 0000 on the next clock edge, i.e.,
the outputs of all flip-flops are currently 1 (maximum count value).

54. Counters with Parallel Load

55. A counter with parallel-load capability
[ Figure 5.24 from the textbook ]

56. How to load the initial count value1
Set the initial count on
the parallel load lines
(in this case 5).

57. How to zero a counter 1 1 Set "Load" to 1, to open the1
Set "Load" to 1, to open the
"1" line of the multiplexers. 1

58. How to zero a counter 1 1 1 When the next positive edge of1 1
When the next positive edge of
the clock arrives, the outputs
of the flip-flops are updated. 1

59. Reset Synchronization

60. Motivation An n-bit counter counts from 0, 1, …, 2n-1
For example a 3-bit counter counts up as follow
0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, …
What if we want it to count like this
0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, …
In other words, what is the cycle is not a power of 2?

61. What does this circuit do?
[ Figure 5.25a from the textbook ]

62. A modulo-6 counter with synchronous reset
Enable Q 1 2 D
Load
Clock 3 4 5
Count
(a) Circuit
(b) Timing diagram
[ Figure 5.25 from the textbook ]

63. A modulo-6 counter with asynchronous resetQ
Clock 1 2
(a) Circuit
Count
(b) Timing diagram 3 4 5
[ Figure 5.26 from the textbook ]

64. A modulo-6 counter with asynchronous resetQ
Clock 1 2
(a) Circuit
Count
(b) Timing diagram 3 4 5
The number 5 is displayed
for a very short amount of time
[ Figure 5.26 from the textbook ]

65. Other Types of Counters (Section 5.11)

66. A two-digit BCD counter
2: Parallel-load four-bit counter
Figure 5.24
Each counts in binary
0-9
Resets generated on 9
Reset by loading 0’s
Second digit enabled by a 9 on first counter

67. A two-digit BCD counter
[ Figure 5.27 from the textbook ]

68. A two-digit BCD counter
What is this?
[ Figure 5.27 from the textbook ]

69. It is a counter with parallel-load capability
[ Figure 5.24 from the textbook ]

70. It is a counter with parallel-load capability
In this case,
the z output is ignored
[ Figure 5.24 from the textbook ]

71. A two-digit BCD counter

72. A two-digit BCD counter

73. Zeroing the BCD counter1 1 1 1 1
Setting "Clear" to 1,
zeroes both counters.
[ Figure 5.27 from the textbook ]

74. Zeroing the BCD counter1 1 1 1 1
Setting "Clear" to 1,
zeroes both counters.
[ Figure 5.27 from the textbook ]

75. How to zero a counter Set all parallel load input lines to zero.
Set all parallel load
input lines to zero.
[ Figure 5.24 from the textbook ]

76. How to zero a counter Set "Load" to 1, to open the
Set "Load" to 1, to open the
"1" line of the multiplexers. 1
[ Figure 5.24 from the textbook ]

77. How to zero a counter When the positive edge of the
When the positive edge of the
clock arrives, all outputs
are set to zero together. 1
[ Figure 5.24 from the textbook ]

78. When Clear = 0 When "Clear" is equal to 0,
When "Clear" is equal to 0,
the two OR gates depend only
on the feedback connections.
[ Figure 5.27 from the textbook ]

79. Enabling the second counter
[ Figure 5.27 from the textbook ]

80. Enabling the second counter
The counter for the most
significant digit is disabled
most of the time.

81. Enabling the second counter1 1
The counter for the most
significant digit is disabled
most of the time.

82. Enabling the second counter2 1
The counter for the most
significant digit is disabled
most of the time.

83. Enabling the second counter3 1
The counter for the most
significant digit is disabled
most of the time.

84. Enabling the second counter4 1
The counter for the most
significant digit is disabled
most of the time.

85. Enabling the second counter5 1
The counter for the most
significant digit is disabled
most of the time.

86. Enabling the second counter6 1
The counter for the most
significant digit is disabled
most of the time.

87. Enabling the second counter7 1
The counter for the most
significant digit is disabled
most of the time.

88. Enabling the second counter8 1
The counter for the most
significant digit is disabled
most of the time.

89. Enabling the second counter9 1 1 1
It is enabled only when
the first counter is at 9.

90. Enabling the second counter9 1 1 1 1
At the same time the first
counter is reset.

91. Enabling the second counter1 1
At the same time the first
counter is reset.

92. Enabling the second counter1 1 1 1

93. Enabling the second counter2 1 1 1

94. . . .

95. Enabling the second counter8 1 1 1

96. Enabling the second counter9 1 1 1 1 1 1

97. Enabling the second counter2 1

98. Enabling the second counter1 1 2 1

99. . . .

100. Enabling the second counter8 1 9 1

101. Enabling the second counter9 1 1 1 1 9 1

102. Enabling the second counter9 1 1 1 1 9 1 1 1

103. Enabling the second counter

104. Enabling the second counter1 1

105. Ring Counter

106. How to build a 4-bit ring counterQ Q Q Q 1 2 3 In D Q D Q D Q D Q
Out Q Q Q Q
Clock
To build a ring counter we start with a shift register.

107. How to build a 4-bit ring counterQ
Clock In
Out 1 2 3
Next, add a loop from the last flip-flop to the first…

108. How to build a 4-bit ring counterQ
Clock
Out 1 2 3
... and remove the In input line.

109. How to build a 4-bit ring counterQ
Clock
Out 1 2 3
Start
Also, add a start input that goes inverted to preset_n of
the first flip=flop and to clear_n of all remaining flip-flops.

110. How to build a 4-bit ring counterQ
Clock
Out 1 2 3
Start
Finally, extend the output lines that form the count number.

111. How to build a 4-bit ring counterQ
Clock
Out 1 2 3
Start
This is the final circuit diagram.

112. 4-bit ring counter
There is only one 1 on the outputs of the four flip-flops
The counting sequence is: 1000, 0100, 0010, 0001, 1000, …
To reset the counter
set start to 1 for a short period of time
This sets the four outputs to 1000

113. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
To initialize the counter set Start to 1.

114. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
After the NOT gate, this 1 goes as 0 to preset_n of
the first flip-flop and to clear_n of all remaining flip-flops.

115. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
This sets the output pattern to 1000,
i.e., only the first bit is one and the rest are zeros.

116. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
Setting Start to 0 has no effect on the outputs,
because both preset_n and clear_n are sensitive only to 0.

117. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
The initialization does not depend on the clock since both
preset_n and clear_n bypass the gates of the latches in the flip-flops.

118. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
That last 0 loops back to the D input of the first flip-flop.

119. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
Clock
Start
time

120. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
Clock
Start
time

121. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
Clock
Start
time

122. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
Clock
Start
time

123. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
Clock
Start
time

124. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
Clock
Start
time

125. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
Clock
Start
time

126. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
Clock
Start
time

127. 4-bit ring counter: How does it work1 D Q
Clock
Out 2 3
Start
It is back to the start of the counting sequence,
which is: 1000, 0100, 0010, 0001.

128. n-bit ring counter
[ Figure 5.28a from the textbook ]

129. Ring Counter (alternative implementation)

130. Alternative version of a 4-bit ring counter
This implementation uses 2-bit up-counter followed by a 2-to-4 decoder.
The counter cycles through 00, 01, 10, 11, 00, …
Recall that the outputs of the decoder are one-hot encoded. Thus, there is only one 1 on its outputs.
Because the output of the counter is the input to the decoder, the outputs of the decoder cycle through: 1000, 0100, 0010, 0001, 1000, …
This is the counting sequence for a ring counter.

131. Alternative version of a 4-bit ring counter
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
[ Figure 5.28b from the textbook ]

132. What are the components?
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock

133. 2-Bit Synchronous Up-Counter
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock

134. 2-Bit Synchronous Up-CounterQ
Clock 1
Clear_n

135. 2-to-4 Decoder with Enable Input
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
[ Figure 5.28b from the textbook ]

136. 2-to-4 Decoder with Enable Input
[ Figure 4.14c from the textbook ]

137. 2-to-4 Decoder with Enable Input1
(always enabled in this example)
[ Figure 4.14c from the textbook ]

138. How Does It Work? Q y 2-to-4 decoder w En Clock 2-bit up-counter Start
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
[ Figure 5.28b from the textbook ]

139. How Does It Work?
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
0 0 1
To initialize this circuit set Start to 1, which sets the counter to 00.

140. How Does It Work?
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
0 0 1
This sets the outputs of the decoder to the start of the counting sequence.

141. How Does It Work?
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
0 0 1
When Start is equal to 0, clear_n has no effect.

142. How Does It Work? 1 0 0 0 0 0 1 Q y 2-to-4 decoder w En Clock
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
0 0 1

143. How Does It Work?
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
0 1 1
The counter increments the count on the positive clock edge ...

144. How Does It Work?
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
0 1 1
… this updates the outputs of the decoder (which are one hot encoded).

145. How Does It Work? 0 1 0 0 0 1 1 Q y 2-to-4 decoder w En Clock
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
0 1 1

146. How Does It Work? 0 0 1 0 1 0 1 Q y 2-to-4 decoder w En Clock
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
1 0 1

147. How Does It Work? 0 0 1 0 1 0 1 Q y 2-to-4 decoder w En Clock
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
1 0 1

148. How Does It Work? 0 0 0 1 1 1 1 Q y 2-to-4 decoder w En Clock
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
1 1 1

149. How Does It Work? 0 0 0 1 1 1 1 Q y 2-to-4 decoder w En Clock
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
1 1 1

150. It is back to the start of the counting sequence,
How Does It Work?
clear_n
2-bit up-counter
Start w En y 1 2 3 Q
2-to-4 decoder
Clock
0 0 1
It is back to the start of the counting sequence,
which is: 1000, 0100, 0010, 0001.

151. Johnson Counter

152. How to build a 4-bit Johnson counterQ
Clock In
Out 1 2 3
To build a Johnson counter start with a shift register.

153. How to build a 4-bit Johnson counterQ
Clock In
Out 1 2 3
Next, add a loop from the Q output of the last flip-flop to the first…

154. How to build a 4-bit Johnson counterQ
Clock
Out 1 2 3
... and remove the In input line.

155. How to build a 4-bit Johnson counterQ
Clock
Out 1 2 3
Reset_n
Also, add a Reset_n line that goes to clear_n of all flip-flops.

156. How to build a 4-bit Johnson counterQ
Clock
Out 1 2 3
Reset_n
Finally, extend the output lines that form the count number.

157. How to build a 4-bit Johnson counterQ
Clock
Out 1 2 3
Reset_n
This is the final circuit diagram.

158. 4-Bit Johnson Counter Only 1-bit changes at a time
Start with a reset of all flip-flops
The counting sequence is: , 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000
An n-bit Johnson counter has a counting sequence of length 2n

159. Initialization: How does it work?Q
Clock
Out 1 2 3
Reset_n

160. Initialization: How does it work?Q
Clock
Out 1 2 3
Reset_n
To initialize the Johnson counter set Reset_n to 0 ...

161. Initialization: How does it work?D Q
Clock
Out 1 2 3
Reset_n
... this zeros the outputs of all flip-flops ...

162. Initialization: How does it work?D Q
Clock
Out 1 2 3
Reset_n
... and also sets the Q output of the last flip-flop to 1.

163. Counting: How does it work?D Q
Clock
Out 1 2 3
Reset_n

164. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
To start counting, Reset_n needs to be set to 1.

165. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

166. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

167. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

168. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

169. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

170. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

171. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

172. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

173. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

174. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

175. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

176. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

177. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

178. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

179. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

180. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
Clock
Reset_n
time

181. Counting: How does it work?1 D Q
Clock
Out 2 3
Reset_n
It is back to the start of the counting sequence, which is:
0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001.

182. n-bit Johnson Counter
[ Figure 5.29 from the textbook ]

183. Timing Analysis of Flip-Flop Circuits (Section 5.15)

184. Timing Review
tsu: setup time
th: hold time
tcQ: propagation delay

185. Timing Example tsu: 0.6ns th: 0.4ns tcQ: 0.8ns to 1.0ns
Which value to use?
Logic gate delay: 1+0.1k
k is equal to the number of inputs
Tmin = tsu + tcQ + tnot = = 2.7ns
Fmax = 1/Tmin = MHz
Check for hold violations
Fastest Q can change = tcQ + tnot = = 1.9ns
1.9ns > 0.4ns therefore no hold violations

186. Timing Example: 4-bit counter
[ Figure 5.67 from the textbook ]

187. Timing Example: 4-bit counter
Look for longest path
Q0 to Q3
Propagation delay of Q0
3 AND propagation delays
1 XOR propagation delay
Setup delay for Q3
Tmin = (1.2) = 6.4ns
Fmax = 1/6.4ns = MHz
Check for hold violations
Fastest Q can change = tcQ + tXOR = = 2ns
2.0ns > 0.4ns therefore no hold violations

188. Timing Example: Clock Skew
Figure A general example of clock skew.

189. Skew Timing Example: 4-bit counter
Q3 now has a clock slew delay: 1.5ns
T = (1.2) = 4.9ns
Now might not be the longest path
Check Q0 to Q2
T = (1.2) = 5.2ns
Fmax = 1/5.2ns = MHz

190. Example 5.22

191. Faster 4-bit Counter Want to increase the speed of the 4-bit counter
Use a similar method as the one used in 4-bit adder
Replace the series of 2-input AND gates with AND gates with more input lines.

192. A faster 4-bit counter
[ Figure 5.75 from the textbook ]

193. Faster 4-bit Counter Longest path: Q0 to Q3
Tmin = tcQ0 + tAND + tXOR + tsu = = 4.2ns
Fmax = 1/4.2ns = MHz > MHz

194. Reaction Timer Circuit (Section 5.14)

195. Problem Statement Want to design a reaction timer
The circuit turns on a light (LED)
A person then presses a switch
Measure the elapsed time from when the LED is turned on until the switch is pressed

196. Clock Divider Input: 102.4kHz Output: 100Hz 10-bit Counter to divide
Output Frequency = 102.4k / 210 = 100Hz

197. A reaction-timer circuit
[ Figure 5.61 from the textbook ]

198. Functionality of circuit
Push switch
Nominally 1
DFF to keep track of the state
Two-digit BCD counter
Output goes to converters to a 7-segment display
Start-up
Assert the Reset signal
Clears counter
Clears flip-flop
Assert w=1 for one cycle
Once switch is hit
Stops counting

199. Push-button switch, LED, and 7-segment displays
[ Figure 5.61c from the textbook ]

200. Examples of Solved Problems (Section 5.17)

201. Example 5.18

202. Circuit for Example 5.18
[ Figure 5.70 from the textbook ]

203. Example 5.19

204. Circuit for Example 5.19
[ Figure 5.71 from the textbook ]

205. Summary of the behavior of the circuit
[ Figure 5.72 from the textbook ]

206. Example 5.20

207. Vending Machine Example
Inputs N, D, Q, Coin, Resetn
N, D, Q: nickel, dime, quarter
Coin: pulsed when a coin is entered
Used to store values into register
Resetn: resets the register value to zero
Add up new coin with old value
Store new sum into old value register
See if total is above thirty cents
If so output Z goes high

208. Circuit for Example 5.20
[ Figure 5.73 from the textbook ]

209. Questions?

210. THE END