1. Latches and Flip-flops
Memory Devices
Latches and Flip-flops

2. Clocks Regular Pulses of High and Low Voltage Triggers memory elements
on level (high or low)
on edge (rising or falling)
high level
One Clock Cycle
rising edge
falling edge
low level

3. S-R Latch (Set - Reset)
High
Low
Set
Reset R Q
~ Q S

4. D Latch (Data Latch)
Clock Q
~ Q
Data In

5. Flip-Flop (Falling Edge Trigger)
Data
D-Latch Q D C
D-Latch Q D C ~Q
Clock
How many transistors?

6. Register Storage for a string of bits
number of bits in general register is word size
Implemented as one flip-flop for each bit
Output
output lines are always available to be read
general registers commonly selected by multiplexors
Input
new values may be saved only when signaled by clock
select or enable line may control clock line
general registers commonly selected for write by decoder

7. Register 8 bit example Data Out Clock Select 8 8 Data In D Q D Q D Q D

8. Register file 4 registers
To MUX
Clock 8 D C Q 8 D Q D Q D Q D Q D Q D Q D Q D Q C C C C C C C C 8 D C Q 8 D C Q
From Decoder
Data In 8

9. 32x32 M U X 5x32 D e c o d %x r 5 32x32 M U X Data In 5 32 5 32 32
Clock
Enable 32

10. MIPS Register file Reg 1 Read 5 Read Data 1 32 Reg 2 Read 5 Reg Write
Write Data 32
Clock
Write Enable