1. 332:437 Lecture 12 Finite State Machine Design
Hardware design approach
Mealy and Moore Machines
Edge-Triggered Flip-Flops
State Machine Analysis
State Machine Synthesis
Summary
Material from An Engineering Approach to Digital Design, by William I. Fletcher, Prentice-Hall Inc.
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2. Suggested Hardware Design Approach
Break circuit design into multiple functional blocks
Optimize each block into a 2-level or multi-level logic form (K-map, Variable-entered map, Synopsys, etc.)
Check for acceptable propagation delay in the system, and go back to Steps 1 and 2 for redesign, if necessary
Use a redundant logic identification to find unnecessary logic and remove it
For a
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3. Bushnell: Digital Systems Design Lecture 12
State Machine Design
Sequential logic, circuits, or machines:
Have internal memory
Types:
Synchronous (clocked) – memory elements controlled by an external signal – can change only at specific times
Asynchronous – less frequently used but more interesting – memory elements change state whenever 1 or more inputs change – no clock
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State Machine Design
VERY IMPORTANT: Control conditions under which state changes
Otherwise single input change causes many state changes, due to relative logic delays
Asynchronous Logic:
Faster than synchronous for small circuits
Slower than synchronous for large circuits
REASON: Vastly more logic is required due to absence of CLOCK
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5. Bushnell: Digital Systems Design Lecture 12
Mealy Machines
Circuit
Outputs (present)
Mealy Machine X
Present
Inputs Z
Output
Decoder
Z = f (X, St)
Next State
Decoder St
Next
State
Present
State
Memory Devices
Or State
St+1 = g (X, St)
Clock
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Moore Machines
Circuit
Outputs (present) Z
Output
Decoder
Present
Inputs
Z = f (St) X
Next State
Decoder St
Next
State
Present
State
Memory Devices
Or State
St+1 = g (X, St)
Clock
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Mealy Machines
Nasty to design reliably and debug
WHY?
Real circuits have hazards:
Undesirable: You expect c to be 0, and run it as input to a flip-flop which catches the short logic 1 pulse on c (called one’s catching)
Flip-flop gets set, but you expected it to be cleared a c b a b
hazard c
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Hazards
Unavoidable
Different signals have different propagation delays
Different paths through circuit
Different logic gates have different delay times – determined by:
Gate type
Number of inputs
Mealy machines do not filter out hazards, from inputs to outputs
WHY? Output decoder is a function of inputs as well as of state
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9. Hazards Propagating Through Output Decoder
Timing diagram: Xi Zk
Sjt
Clock Xi
Sjt Zk
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Moore Machine
Output is stable:
Filters out hazards in primary outputs, since they cannot propagate from inputs to outputs
Rule: Never design a Mealy Machine unless you really have to
Unfortunately, you often have to do it to satisfy the circuit functional specification
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11. State Machine Design Process
Identify State Variables S
Identify Output Decoder & Next State Decoder
Build State Transition Diagram
Minimize States
Choose appropriate type of flip-flops
Choose State Assignment
Assignment of binary codes to machine states
Design next state decoder & output decoder – use combinational logic structured design methods – K-maps, Variable-Entered Map, Verilog
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12. Mealy Machine Sequence Detector Recognizing 1102
Double circle shows reset state S1 S2 S3
0/1
1/0
0/0
Present State S1 S2 S3
S1/0
S1/1 1
S2/0
S3/0
Present Input X/Z
X/Z
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Bushnell: Digital Systems Design Lecture 12

13. Moore Machine Sequence Detector Recognizing 1102
Pay for better behavior of Moore machine with extra flip-flop
S1/0
S2/0 1
S4/1
S3/0
Present State S1 S2 S3 S4 1
Present
Input Z
Output
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14. Bushnell: Digital Systems Design Lecture 12
Flip-Flops
Cross-coupled NOR/NAND latches
Clocked Master-Slave Flip-Flop (Pulse or level-triggered) Q /R /S
00 for /R & /S
not allowed Q
11 for R & S
not allowed R S
Master latch
Slave latch Q S R CP 1 2 3 4 5 6 7 8
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Bushnell: Digital Systems Design Lecture 12

15. One’s Catching Problem
Timing Diagram shows problem
Master starts oscillating
If too close to clock falling edge, Slave might record a 0, not a 1 CP S R
Enable
1 & 2
Disable
Setup
Hold
5 & 6
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Bushnell: Digital Systems Design Lecture 12

16. Edge-Triggered Flip-Flop
Sensitive only to input changes around rising clock edge (positive edge-triggered)
Setup and Hold times
Less likely to catch a 0 or 1
Characteristic Table: D 1 Qt 1
Qt+1 1
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17. Edge-Triggered Flip-Flop State Transition DiagramC
Forces S & R
to 1
Forces B to 0
A to 1
Forces R High
S Low
Sets FF
Forces B to 1
A to 0
Forces S High
R Low
Resets FF
D = 0
D = 1 C
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18. Edge-Triggered Flip-Flop Logic CircuitQ /S C D /R A B
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19. Sequential Circuit Analysis
Identify inputs (X’s), outputs (Z’s), coded states (Y’s)
Obtain output equations Z = F (X, Y)
Obtain Flip-Flop excitation equations Di = Gi (X, Y)
Construct Excitation Table from excitation equations for all possible output states
Construct Next State Table from Excitation Table
Merge output functions to Next State Table
Form Coded State Transition Table
Construct State Transition Table from Coded State Transition Table
Construct State Transition Diagram
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20. Example – Mealy Machine
CLK K2 Q2 J2 K1 Q1 J1 z 1 2 4 3 5
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Analysis
z is output
y1 and y2 are state variables – maximum of 4 states
X = [x = 0, x = 1]
Z = [z = 0, z = 1]
Y = [y1y2 = 00, 01, 10, 11]
Output Equations z = xy1
Flip-Flop Excitation Equations
J1 = x y J2 = x y1
K1 = y1 + y K2 = x y1
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Analysis (continued)
Evaluate J1, K1, J2, K2 under all possible inputs
Flip-Flop Excitation Table
J1K1,J2K2,z
y1y2 00 01 11 10
00,01,0
11,01,0
11,10,0
01,10,0 1
10,10,0
01,11,1
11,11,1 x
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Analysis (continued)
Apply JK FF Characteristic Table to Flip-Flop Excitation Table to get Next State Table
y1y2 00 01 11 10 1 x
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Analysis (continued)
Create Coded State Transition Table
Merge in Present Output
y1y2 00 01 11 10
00/0
10/0
01/0 1
11/0
00/1
01/1
x/z
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Analysis (continued)
Create State Transition Table
Name the states – each distinct combination of y1y2
y1y2 00 01 11 10
a/0
d/0
b/0 1
c/0
a/1
b/1
x/z
State a b c d
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Analysis (concluded)
Use State Transition Table to create State Transition Diagram
State b – recognized ’s
O/P high
State a – recognized ’s a b c d
0/0
1/0
1/1
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27. State Machine Synthesis
Same steps as analysis, but in reverse
Write accurate word description of the problem.
“Build a machine that will produce 1 on the output z when 4+ consecutive 1’s occur on x after at least one 0 input has occurred.”
Form State Transition Table
State Reduction
If 2 states a & b have same output sequence when started in a & b for any input sequence, they are equivalent states
Outputs & next states must be same
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28. Synthesis (continued)
Make state assignment
Problems:
No known general procedure gives minimal cost
Make all unused states transition to idle state under all input conditions
Avoids state trapping in illegal state
Make Coded State Transition Table
Choose Flip-Flop Type
For SSI, MSI, LSI JK works best – simplifies Next State & Output decoders
For VLSI and ULSI, Use D flip-flops
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Synthesis (concluded)
Obtain Flip-Flop Excitation Tables
Complete & Minimize Flip-Flop Excitation Equations
Complete & Minimize Flip-Flop Output Equations
Complete Sequential Circuit Design
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Example 1 2 3 4 5 6 7
0/0
1/0
1/1
Produce 1 on z output after 4+ consecutive 1’s on input x after at least one 0 input on x
Assume that x is synchronized with the clock
State Diagram – Mealy Machine
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31. Final State Transition Table1 2 3 4 5 6 7
2/0
7/0
3/0
4/0
5/0
6/1 x
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State Reduction
# Flip-Flops = log2 (# states)
States 5 & 6 are equivalent
States 1 & 7 are equivalent
Reduced State Transition Table
State 1 2 3 4 5
2/0
1/0
3/0
4/0
5/0
5/1 x
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State Assignment
Assign binary codes to state names
State 1 2 3 4 5 y1 y2 y3
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34. Coded State Transition Table1 2 3 4 5
001/0
XXX/X
000/0
011/0
010/0
110/0
110/1 y1 y2 y3 x
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35. Flip-Flop Selection and Output Decoder
Select D flip-flops
Flip-Flop Excitation Table
Output Karnaugh Map
z = x y1 Qt 1
Qt+1 D
y1x
y2y3 00 01 11 10
X X X 1
X X X 0
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36. K-Maps for Next State Decoder
y1x
y2y3 00 01 11 10 1
X X X
X X X 0 D1
y1x
y2y3 00 01 11 10 1
X X X
X X X 0 D2
y1x
y2y3 00 01 11 10 1
X X X
X X X 1 D3
D1 = x y2 y3
D2 = x y3 + x y2 = x (y2 + y3)
D3 = x + y2 y3
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Final Machine x y2
CLK C Q2 D2 y3 z y1 Q3 D3 Q1 D1
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Problems
No way to initialize machine – comes up in randomly-chosen state in real hardware
SOLUTION: Add reset line and initialize all flip-flops
If machine fails during operation & goes into undefined state, no guarantee that it will ever reenter a legal state
SOLUTION: Design next state decoder so that a path always exists from undefined states to legal states
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Problems (continued)
Sequential Machines cannot be tested
SOLUTIONS:
Choose state assignment to allow testing
Add test mode to guarantee initializing sequence for all states
SCAN design – in test mode, all flip-flops become a giant shift register
Can shift in and shift out states
Partial SCAN Design – Apply Method 3 only to selected flip-flops
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40. Corrected State Machine Design1 2 3 4 5 7
0/0
1/0
X/X
1/1 8 6
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41. Corrected State Transition Table1 2 3 4 5 6 7 8
2/0
1/0
3/0
4/0
5/0
5/1 x
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42. Improved Coded State Transition Table1 2 3 4 5 6 7 8
001/0
000/0
011/0
010/0
110/0
110/1 y1 y2 y3 x
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Changed Karnaugh Maps
y1x
y2y3 00 01 11 10 1
0 0 0 D1
y1x
y2y3 00 01 11 10 1
0 0 0 D2
y1x
y2y3 00 01 11 10 1
0 0 0 D3
y1x
y2y3 00 01 11 10 00 01 11
0 0 0 1 10 z
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Changed Equations
D1 = x y2 y3
D2 = x y2 y3 + x y1 y3
D3 = x y1 + y1 y2 y3 + x y2 y3
z = x y1 y2 y3
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45. Improved Logic Diagramx y2
CLK C Q2 D2 y1 y3 z Q3 D3 Q1 D1
reset
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46. Implementation Comparisons
Old Implementation
1 3-input AND
3 2-input AND
2 2-input OR
Inverter
New Implementation
1 4-input AND
4 3-input AND
1 2-input AND
1 3-input OR
2 2-input OR
Inverter
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Summary
Hardware design approach
Mealy and Moore Machines
Edge-Triggered Flip-Flops
State Machine Analysis
State Machine Synthesis
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Bushnell: Digital Systems Design Lecture 12