1. Registers and Counters
Mano & Ciletti
Chapter 6
By Suleyman TOSUN Ankara University

2. Outline Registers Shift registers Ripple counters Synchronous counters
Other counters

3. Registers A group of flip-flops
Each is capable of storing one bit of information
n-bit registers can store n bits (n flip-flops)
At each clock, the binary data available at the inputs of flip-flops are transferred to the registers.
When Clear=0, all flip-flops are reset
It clears the registers making all stored values as 0’s.
When Clear=1, input data can be stored in the registers.

4. Registers with Parallel Load
Synchronous systems have a master clock.
All operations are synchronized with it.
If we want to select the registers to execute, a separate control must be used:
The transfer of new info to the registers is called loading or updating.
If all the flip-flops are loaded simultaneously, loading is done in parallel.

5. Clock Gating If we do not want to change the content of a register:
The inputs must be held constant OR
Clock must be inhibited from the circuit (clock gating).
Clock gating adds additional delay (propagation delay).
Clock reaches unevenly to different part of the circuit.
As a result, we loose the synchronous behavior.
Use D inputs rather than C inputs of the flip-flops to control the register. 1
clock
clock
clock

6. Registers with Parallel Load
Additional gates in the figure is two channel mux
When load=1, data (Ii) goes to D input.
Load the register
When load=0, register outputs (Ai) goes to D input
No change (do not load the register)

7. Shift Registers
A register that is capable of shifting the binary information to the neighboring cell
In a selected direction
Chain of flip-flops
Output of one register connected to the input of the next.

8. Serial Transfer
In serial mode when information is transferred one bit at a time.
Shifting the bits from source register to the destination register.
Shifting can be controlled by controlling the clock (clock gating)
Problematic

9. Serial Transfer from Reg. A to Reg. B

10. Serial Addition Parallel operations are faster
Serial operations are slower BUT
Requires less hardware
Less silicon area on a chip

11. Serial Adder

12. Serial Adder with JK Flip-Flops
Q represents Cin (present state) and Cout (next state)
Design a 1-bit serial adder with JK flip-flops

13. Serial Adder with JK Flip-Flops

14. Universal Shift Registers
The information entered serially to the registers
They can be taken in parallel.
Opposite is possible
Information can be entered in parallel
And can be taken in serially (shifting)
Some shift registers have input/output terminals for parallel transfer.
They also have shift-left and shift right capabilities.

15. Universal Shift Register

16. Universal Shift Register

17. Counters A register that goes through prescribed sequence of states.
Input pulses can be
Clock pulse OR
External source
Sequence can be
Binary OR
Any sequence we specify
n-bit counter has n flip-flops
It can count from 0 to 2n-1.
Two types of counters
Ripple Counters
Synchronous counters

18. Ripple Counters Series of flip-flop connection
Output of one is connected to C input (clock input) of the next.
They can be implemented with
JK flip-flops by tying up J and K inputs
T flip-flops
D flip-flops, by using complement output.

19. Ripple Counters Up ripple counter Down ripple counter
Use negative edge triggered
Down ripple counter
Use positive edge triggered

20. BCD Ripple Counter Sequence of 10 states (from 0 to 9)
Needs 4 flip-flops
Similar to binary counter
Except that the state after 1001 is 0000.

21. Decade Counter Q1 changes state after each clock pulse.
Q2 complements every time Q1 goes from 1 to 0, AS LONG AS Q8=0.
When Q8 becomes 1, Q2 remains at 0.
Q4 complements every time Q2 goes from 1 to 0.
Q8 remains at 0 as long as Q2 or Q4 is 0.
When both Q2 and Q4 become 1, Q8 complements when Q1 goes from 1 to 0.

22. Three Decade Counter To count from 0 to 999 Use three decade counter
Input to next decade counter is coming from Q8.
When Q8 goes from 1 to 0, it triggers the next counter.

23. Synchronous Counters
Clock pulses applied to the C inputs of all flip-flops
All flip-flops triggered simultaneously.
Flip-flops are complemented when
J=1 and K=1
T=1

24. Binary Counter Least significant bit is always complemented.
Others are complemented when ALL previous inputs are 1.

25. Up-down binary counter
When up=1, count upwards
When down=1 and up=0, count downwards
When both are 0, do not change the count.

26. BCD counter

27. Counters with unused states