1. CENG 241 Digital Design 1 Lecture 11
Amirali Baniasadi

2. This Lecture Review of last lecture: Analysis
Chapter 5: State Reduction, Design Procedure

3. Analysis of Clocked Sequential Circuits
Analysis: Obtaining a table/diagram for the time sequence of inputs/outputs/internal states.
Examples: State Equations, State Table, State Diagram

4. Analysis of Clocked Sequential Circuits
Example of state equation:
A(t+1) = A(t)x(t) + B(t)x(t)
B(t+1) = A’(t)x(t)
A(t+1)=Ax+Bx
B(t+1)=A’x
y(t)=(A(t)+B(t)).x’(t)
= (A+B)x’

5. Example of state tables
Present state input Next State Output
A B x A B y
State equation:
A(t+1) = A(t)x(t) + B(t)x(t)
B(t+1) = A’(t)x(t)
y(t)=(A(t)+B(t)).x’(t)

6. Example of state tables-2nd form
Present state Next State Output
x= x= x=0 x=1
AB AB AB y y
State equation:
A(t+1) = A(t)x(t) + B(t)x(t)
B(t+1) = A’(t)x(t)
y(t)=(A(t)+B(t)).x’(t)

7. Example of state diagram
Present state Next State Output
x= x= x=0 x=1
AB AB AB y y

8. Mealy & Moore
Mealy machine: Output depends on both input & present state
Moore machine: Output only depends on present state.

9. Example of Mealy Machine
Present state Next State Output
x= x= x=0 x=1
AB AB AB y y

10. Example of Moore Machine
Present state input Next State
A B x A B

11. State Reduction and Assignment
Goal: Reduce the number of states while keeping the external input-output requirements.
2m states need m flip-flops, so reducing the states may reduce flip-flops.
If two states are equal, one can be removed but what are equal states?

12. State Reduction Example
As an example consider the input sequence below:
applied and start from state a.
State a a b c d e f f g f g a
input
output

13. State Reduction Example
Present State Next State Output
x= x= x= x=1
a a b
b c d
c a d
d e f
e a f
f g f
g a f
States e and g are equal since for each member of the set of
inputs, they give the same output and send the circuit either to
the same state or an equivalent state.

14. State Reduction Example
Present State Next State Output
x= x= x= x=1
a a b
b c d
c a d
d e f
e a f
f e f
NEW equal states: d and f
Table and state diagram after the first reduction: g is removed and replaced by state e.

15. State Reduction Example
Present State Next State Output
x= x= x= x=1
a a b
b c d
c a d
d e d
e a d
If we apply the same sequence
State a a b c d e d d e d e a
input
output
Table and state diagram after the second reduction: f is removed and replaced by state d.

16. Design Procedure
First Step: From the word description of the problem derive a state diagram
example:design a circuit to detect three or more consecutive 1’s in a string of bits
coming through an input line.

17. Design steps 1.From word description, derive state diagram
2.Reduce the number of states
3.Assign binary values to states
4.Obtain the binary coded state table
5.Choose the type of flip-flop used
6.Derive the simplified flip-flop input and output equations
7.Draw the logic diagram
steps 4 to 7can be implemented by exact algorithms and can be automated.
The part of the design that is well-defined is referred to as synthesis.

18. State Table for Sequence Decoder
Present State Input Next State Output
A B x A B y
A(t+1)= Σ(3,5,7)
B(t+1)= Σ(1,5,7)
Y(A,B,x)= Σ(6,7)

19. Synthesis Using D Flip-Flops
A(t+1)=DA(A,B,x)= Σ(3,5,7)
B(t+1)=DB(A,B,x)= Σ(1,5,7)
Y(A,B,x)= Σ(6,7)

20. Logic Diagram for a Sequence Detector
DA = Ax + Bx
DB= Ax + B’x
y=AB

21. Excitation Tables Using flip-flops other than D can be complicated.
Why? Input equations for the circuit must be derived indirectly from the state table
Excitation tables can help.
Excitation tables give us the flip-flop input for every state transition.
Example : JK- Recall Q(t+1) = JQ’(t) + K’Q(t)
Q(t) Q(t+1) J K X X X X

22. Excitation Tables- T flip-flop
Example : JK- Recall Q(t+1) = TQ’(t) + T’Q(t) = T XOR Q
Q(t) Q(t+1) T

23. Synthesis Using JK Flip-Flops
Present State Input Next State Flip-Flop Inputs
A B x A B JA KA JB KB
x x
x x
x x
x x
x x
x x
x x
x x
We also include J, K input conditions, derived from the excitation table.

24. Synthesis Using JK Flip-Flops

25. Synthesis Using JK Flip-Flops

26. Synthesis Using T Flip-Flops
Example: 3-bit Binary Counter
The counter counts the clock.
Clock does not appear explicitly in the state diagram.

27. Synthesis Using T Flip-Flops
Present State Next State Flip-Flop Inputs
A2 A A A A A TA TA TA0

28. Synthesis Using T Flip-Flops

29. Synthesis Using T Flip-Flops

30. Summary State Reduction, Synthesis Reading up to page 234
Midterm 2: Thursday July 12th 2012
HW 5: Chapter 5- 6, 9, 10,11,12,13, 16, 18 (ignore HDL), 19 (ignore HDL) and 20. Due: Thursday July 19th