1. CPE 528: Session #8
Department of Electrical and Computer Engineering University of Alabama in Huntsville

2. Notes on VHDL Synthesis
Outline
Files
Notes on VHDL Synthesis
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3. File input/output in VHDL Used in test benches
Files
File input/output in VHDL
Used in test benches
Source of test data
Storage for test results
VHDL provides a standard TEXTIO package
read/write lines of text
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4. Files (cont’d)
VHDL defines a file object, associated types, and certain limited file operations
File declarations
VHDL87
VHDL93
TYPE file_type IS FILE OF type_mark;
PROCEDURE READ(FILE identifier : file_type; value : OUT type_mark);
PROCEDURE WRITE(FILE identifier : file_type; value : IN type_mark);
FUNCTION ENDFILE(FILE identifier : file_type) RETURN BOOLEAN;
VHDL defines the file object and includes some basic file IO procedures implicitly after a file type is defined. A file type must be defined for each VHDL type that is to be input from or output to a file.
Example:
TYPE bit_file IS FILE of bit;
In VHDL87, there are no routines to open or close a file, so both the mode of the file and its name must be specified in the file declaration. The mode defaults to read if none is specified.
Examples:
FILE in_file:bit_file IS “my_file.dat” -- opens a file for reading
FILE out_file:bit_file IS OUT “my_other_file.dat”; -- opens a file for writing
In VHDL93, a file can be named and opened in the declaration:
FILE in_file:bit_file OPEN READ_MODE IS “my_file.dat”; -- opens a file for reading
Or simply declared (and named and opened later):
FILE out_file:bit_file;
FILE identifier : file_type IS [mode] “file_name”;
FILE identifier : file_type [[OPEN mode] IS “file_name”];
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5. Files (Cont’d)
VHDL 87 - files are opened and closed when the associated file object comes into and goes out of scope
VHDL 93
-- opens a file for reading
FILE in_file:bit_file IS “my_file.dat”
-- opens a file for writing
FILE out_file:bit_file IS OUT “my_other_file.dat”;
VHDL defines the file object and includes some basic file IO procedures implicitly after a file type is defined. A file type must be defined for each VHDL type that is to be input from or output to a file.
Example:
TYPE bit_file IS FILE of bit;
In VHDL87, there are no routines to open or close a file, so both the mode of the file and its name must be specified in the file declaration. The mode defaults to read if none is specified.
Examples:
FILE in_file:bit_file IS “my_file.dat” -- opens a file for reading
FILE out_file:bit_file IS OUT “my_other_file.dat”; -- opens a file for writing
In VHDL93, a file can be named and opened in the declaration:
FILE in_file:bit_file OPEN READ_MODE IS “my_file.dat”; -- opens a file for reading
Or simply declared (and named and opened later):
FILE out_file:bit_file;
-- opens a file for reading
FILE in_file:bit_file OPEN READ_MODE IS “my_file.dat”;
-- Or simply declared (and named and opened later):
FILE out_file:bit_file;
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6. File Opening and Closing
In VHDL93, files can be opened in the declaration or predefined procedures can be used:
The values for FILE_OPEN_KIND are: READ_MODE, WRITE_MODE, and APPEND_MODE
The values for FILE_OPEN_STATUS are: OPEN_OK, STATUS_ERROR, NAME_ERROR, and MODE_ERROR
PROCEDURE FILE_OPEN(FILE identifier:file_type;
file_name: IN STRING;
open_kind: FILE_OPEN_KIND := READ_MODE);
PROCEDURE FILE_OPEN(status: OUT FILE_OPEN_STATUS;
FILE identifier: file_type;
PROCEDURE FILE_CLOSE(FILE identifier: file_type);
In VHDL87, the file is opened and closed when it come into and goes out of scope.
In VHDL93, there are two FILE_OPEN procedures, one of which returns a value of the status (success) for opening the file, and one which doesn’t. There is also a FILE_CLOSE procedure.
The values for FILE_OPEN_KIND are:
READ_MODE,
WRITE_MODE, and
APPEND_MODE.
The values for FILE_OPEN_STATUS are:
OPEN_OK,
STATUS_ERROR,
NAME_ERROR, and
MODE_ERROR.
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7. Basic file operations in VHDL are limited to unformatted input/output
Text Input and Output
Basic file operations in VHDL are limited to unformatted input/output
VHDL includes the TEXTIO package for input and output of ASCII text
TEXTIO is located in the STD library
The following data types are supported by the TEXTIO routines:
Bit, Bit_vector
Boolean
Character, String
Integer, Real
Time
USE STD.TEXTIO.ALL;
The TEXTIO package provides additional declarations and subprograms for handling text (ASCII) files in VHDL. For example, the basic READ and WRITE operations of the FILE type are not very useful because they work with binary files. Therefore, the TEXTIO package provides subprograms for manipulating text more easily and efficiently.
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8. TEXTIO Procedures TEXTIO defines a LINE data type
All read and write operations use the LINE type
TEXTIO also defines a FILE type of TEXT for use with ASCII text
Procedures defined by TEXTIO are:
READLINE(f,k)
reads a line of file f and places it in buffer k
READ(k,v,...)
reads a value of v of its type from k
WRITE(k,v,...)
writes value v to LINE k
WRITELINE(f,k)
writes k to file f
ENDFILE(f) returns TRUE at the end of FILE
TEXTIO defines two new data types to assist in text handling. The first is the LINE data type. The LINE type is a text buffer used to interface VHDL I/O and the file. Only the LINE type may read from or written to a file.
A new FILE type of TEXT is also defined. A file of type TEXT may only contain ASCII characters.
Several of the procedures provided by TEXTIO for handling text input/output are also listed in this slide.
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9. READ and WRITE have several formatting parameters
Using TEXTIO
Reading from a file
READLINE reads a line from the file into a LINE buffer
READ gets data from the buffer
Writing to a file
WRITE puts data into a LINE buffer
WRITELINE writes the data in the LINE buffer to file
READ and WRITE have several formatting parameters
Right or left justification
Field width
Unit displayed (for time)
TEXTIO requires that all disk access go through a buffer of type LINE. In addition, the READ and WRITE procedures can further format the text. The field width of the text is the length of the text if not otherwise specified. If the text is of type TIME, the unit of time can be specified.
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10. TEXTIO: Example 1 This procedure displays the current state of a FSM
USE STD.TEXTIO.ALL; --TEXTIO package is available
TYPE state IS (reset, good); - new type state is declared
PROCEDURE display_state (current_state : IN state) IS
VARIABLE k : LINE; -- buffer k of type LINE
-- file flush is of type TEXT and will output to console
FILE flush : TEXT IS OUT "/dev/tty";
VARIABLE state_string : STRING(1 to 7); -- text value
BEGIN
CASE current_state IS
WHEN reset => state_string := "reset ";
WHEN good => state_string := "good ";
END CASE;
WRITE (k, state_string, LEFT, 7); --left justified, 7s
WRITELINE (flush, k); -- send buffer to file flush
END display_state;
This example displays the current state of a finite state machine model execution. First, the USE clause makes the contents of the TEXTIO package available. The enumerated type STATE is then locally declared. The procedure display_state requires only one input value, the current state of the FSM.
Several local variables are declared within the procedure. The buffer k of type LINE will be used for WRITE storage. The FILE flush is of type TEXT and will output to a file named /dev/tty (i.e. the system console in UNIX; that is, the procedure will write to the screen). The variable state_string holds the text value of the state.
The CASE statement is used to assign the appropriate string value to the variable state_string in preparation for outputting the information to a file. The WRITE statement then writes the value of state_string to the buffer k. The WRITE statement further specifies that the string should be left justified and be 7 spaces wide.
Finally, the WRITELINE sends the buffer k to the file flush. The text is then written to the screen.
Note that this particular procedure would not work well for writing to a file since the file is re-initialized every time the procedure is used, and thus the text would always be written to the beginning of the file. However, using TEXTIO to write to a file may be accomplished by passing the file to the procedure as a parameter, or by using a process that implements the same functionality, for example.
Based on [Navabi93]
If we call this procedure again ...
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11. TextIO: Read_v1d
procedure read_v1d (variable f :in text ; v : out std_logic_vector ) is
variable buf : line;
variable c : character ;
begin do not forget appropriate library declarations
readline (f , buf ); --read a line from the file.
for i in v ’range loop
read( buf , c ) ; --read a character from the line.
case c is
when ‘ X ’ => v (i) := ‘ X ’ ;
when ‘ U ’ => v (i) := ‘ U ’ ;
when ‘ Z ’ => v (i) := ‘ Z ’ ;
when ‘ 0 ’ => v (i) := ‘ 0 ’ ;
when ‘ 1 ’ => v (i) := ‘ 1 ’ ;
when ‘ -’ => v (i):= ‘ -’ ;
when ‘ W ’ => v (i) := ‘ W ’ ;
when ‘ L ’ => v (i) := ‘ L ’ ;
when ‘ H ’ => v (i) := ‘ H ’ ;
when others => v (i) := ‘ 0 ’;
end case;
end loop;
end;
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12. Longer TextIO example -- square the value int_val := int_val **2;
-- write the squared value to the line
WRITE( out_line, int_val);
-- write the line to the output file
WRITELINE( outfile, out_line);
END LOOP;
END PROCESS;
END simple;
LIBRARY IEEE;
USE STD.TEXTIO.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY square IS
PORT( go : IN std_logic);
END square;
ARCHITECTURE simple OF square IS
BEGIN
PROCESS(go)
FILE infile : TEXT IS IN "/pp/test/example1";
FILE outfile : TEXT IS OUT "/pp/test/outfile1";
VARIABLE out_line, my_line : LINE;
VARIABLE int_val : INTEGER;
WHILE NOT( ENDFILE(infile)) LOOP
-- read a line from the input file
READLINE( infile, my_line);
-- read a value from the line
READ( my_line, int_val);
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13. Format of the data in the file
An Example
Procedure to read data from a file and store the data in a memory array
Format of the data in the file
address N comments byte1 byte2 ... byteN comments
address – 4 hex digits
N – indicates the number of bytes of code
bytei - 2 hex digits
each byte is separated by one space
the last byte must be followed by a space
anything following the last state will not be read and will be treated as a comment
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14. An Example (cont’d) Code sequence: an example
12AC 7 (7 hex bytes follow) AE 03 B6 91 C7 00 0C (LDX imm, LDA dir, STA ext) 005B 2 (2 bytes follow) 01 FC_
TEXTIO does not include read procedure for hex numbers
we will read each hex value as a string of characters and then convert the string to an integer
How to implement conversion?
table lookup – constant named lookup is an array of integers indexed by characters in the range ‘0’ to ‘F’
this range includes the 23 ASCII characters: ‘0’, ‘1’, ... ‘9’, ‘:’, ‘;’, ‘<‘, ‘=‘, ‘>’, ‘?’, ‘A’, ... ‘F’
corresponding values: 0, 1, ... 9, -1, -1, -1, -1, -1, -1, -1, 10, 11, 12, 13, 14, 15
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15. VHDL Code to Fill Memory Array
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16. VHDL Code to Fill Memory Array (cont’d)
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17. Notes on VHDL Synthesis
Department of Electrical and Computer Engineering University of Alabama in Huntsville

18. VHDL Packages for Synthesis VHDL for Combinational Logic Synthesis
Outline
VHDL Packages for Synthesis
VHDL for Combinational Logic Synthesis
VHDL for Sequential Logic Synthesis
VHDL for RTL Level Synthesis
Structural VHDL
Implementation Technology Considerations
Summary 6

19. VHDL Packages for Synthesis Base Types
Standard bit types may be used
Typically IEEE 1164 Std. types are used
std_ulogic type
Values ‘U’, ‘X’, ‘W’, and ‘-’ are called metalogical values for synthesis
USE IEEE.std_logic_1164.ALL;
TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care );
std_logic type - resolved std_ulogic type

20. VHDL Packages for Synthesis Base Types (cont.)
The std_logic_1164 package also contains:
Vectors of std_ulogic and std_logic
Subtypes of std_logic - X01, X01Z, UX01, UX10Z
Logic functions with various arguments - std_ulogic, std_logic, std_logic_vector
FUNCTION “and” (l,r : std_ulogic;) RETURN UX01;
FUNCTION “nand” (l,r : std_ulogic;) RETURN UX01;
FUNCTION “or” (l,r : std_ulogic;) RETURN UX01;
FUNCTION “nor” (l,r : std_ulogic;) RETURN UX01;
FUNCTION “xor” (l,r : std_ulogic;) RETURN UX01;
FUNCTION “xnor” (l,r : std_ulogic;) return ux01;
FUNCTION "not" (l,r : std_ulogic) RETURN UX01;
Conversion functions
FUNCTION To_bit(s:std_ulogic) RETURN bit;
FUNCTION To_bitvector(s:std_ulogic_vector) RETURN bit_vector;
FUNCTION To_StdULogic(b:bit) RETURN std_ulogic;

21. VHDL Packages for Synthesis Base Types (cont.)
Clock edge functions
FUNCTION rising_edge (SIGNAL s:std_ulogic) RETURN boolean;
FUNCTION falling_edge (SIGNAL s:std_ulogic) RETURN boolean;
Unknown functions
FUNCTION Is_X (s:std_ulogic_vector) RETURN boolean;
FUNCTION Is_X (s:std_logic_vector) RETURN boolean;
FUNCTION Is_X (s:std_ulogic) RETURN boolean;

22. VHDL Packages for Synthesis Arithmetic Packages
All synthesis tools support some type of arithmetic packages
Synopsis developed packages based on std_logic_1164 package - supported by many other synthesis tools
std_logic_arith
std_logic_signed
std_logic_unsigned
Actel synthesis tools support their own package
asyl.arith
IEEE has developed standard packages for synthesis IEEE Std
Numeric_Bit
Numeric_Std
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23. IEEE Std 1076.3 Packages Numeric_Bit
Type declarations for signed and unsigned numbers
USE IEEE.numeric_bit.ALL;
TYPE unsigned IS ARRAY (natural RANGE <> ) OF bit;
TYPE signed IS ARRAY (natural RANGE <> ) OF bit;
Arithmetic operators - various combinations of signed and unsigned arguments
FUNCTION “abs” (arg:unsigned) RETURN unsigned;
FUNCTION “-” (arg:unsigned) RETURN unsigned;
FUNCTION “+” (l,r:unsigned) RETURN unsigned;
FUNCTION “-” (l,r:unsigned) RETURN unsigned;
FUNCTION “*” (l,r:unsigned) RETURN unsigned;
FUNCTION “/” (l,r:unsigned) RETURN unsigned;
FUNCTION “rem” (l,r:unsigned) RETURN unsigned;
FUNCTION “mod” (l,r:unsigned) RETURN unsigned;
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24. IEEE Std 1076.3 Packages Numeric_Bit
Comparison operators - various combinations of signed and unsigned arguments
FUNCTION “>” (l,r:unsigned) RETURN boolean;
FUNCTION “<” (l,r:unsigned) RETURN boolean;
FUNCTION “<=” (l,r:unsigned) RETURN boolean;
FUNCTION “>=” (l,r:unsigned) RETURN boolean;
FUNCTION “=” (l,r:unsigned) RETURN boolean;
FUNCTION “/=” (l,r:unsigned) RETURN boolean;
Shift and rotate functions
FUNCTION shift_left (arg:unsigned; count:natural) RETURN unsigned;
FUNCTION shift_right (arg:unsigned; count:natural) RETURN unsigned;
FUNCTION rotate_left (arg:unsigned; count:natural) RETURN unsigned;
FUNCTION rotate_right (arg:unsigned; count:natural) RETURN unsigned;
FUNCTION sll (arg:unsigned; count:natural) RETURN unsigned;
FUNCTION slr (arg:unsigned; count:natural) RETURN unsigned;
FUNCTION rol (arg:unsigned; count:natural) RETURN unsigned;
FUNCTION ror (arg:unsigned; count:natural) RETURN unsigned;
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25. IEEE Std 1076.3 Packages Numeric_Bit
Resize functions
FUNCTION resize (arg:unsigned;new_size:natural) RETURN unsigned;
FUNCTION resize (arg:signed;new_size:natural) RETURN signed;
Conversion functions
FUNCTION to_integer (arg:unsigned) RETURN natural;
FUNCTION to_unsigned (arg,size:natural) RETURN unsigned;
Logical operators
FUNCTION “not” (l:unsigned) RETURN unsigned;
FUNCTION “and” (l,r:unsigned) RETURN unsigned;
FUNCTION “or” (l,r:unsigned) RETURN unsigned;
FUNCTION “nand” (l,r:unsigned) RETURN unsigned;
FUNCTION “nor” (l,r:unsigned) RETURN unsigned;
FUNCTION “xnor” (l,r:unsigned) RETURN unsigned;
Edge detection functions
FUNCTION rising_edge(SIGNAL s:bit) RETURN boolean;
FUNCTION falling_edge(SIGNAL s:bit) RETURN boolean;
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26. IEEE Std 1076.3 Packages Numeric_Std
USE IEEE.numeric_std.ALL;
Similar to Numeric_Bit package using std_logic_1164 types
Signed and unsigned type declarations
Aritmetic operators
Comparison operators
Shift and rotate functions
Resize functions
Conversion functions
Logical operators
Match functions
STD_MATCH function compares two values and returns true if:
- both values are well defined and have the same values
- one value is ‘0’ and the other is ‘L’
- one value is ‘1’ and the other is ‘H’
- at least one of the values is ‘-’
For vectors, they must be of the same length and each element returns true from a STD_MATCH call on it.
Translation functions translate ‘H’ to ‘1’ and ‘L’ to ‘0’. If a value other than ‘0’, ‘L’, ‘1’, or ‘H’ is found, a warning is issued.
FUNCTION std_match (l,r:std_ulogic) RETURN boolean;
FUNCTION std_match (l,r:unsigned) RETURN boolean;
Translation functions
FUNCTION to_01 (s:unsigned; xmap:std_logic := ‘0’) RETURN unsigned;
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27. VHDL for Combinational Logic Synthesis
Outline
VHDL Packages for Synthesis
VHDL for Combinational Logic Synthesis
Types
Attributes
Concurrent signal assignment statements
Operators
Processes
If statements
Case statements
Loops
Procedures and functions
Tri state logic
Use of don’t cares
After clauses
Inferring latches
Problems to avoid
VHDL for Sequential Logic Synthesis
VHDL for RTL Level Synthesis 6

28. Types Scalar types Enumeration types are supported
Bit, Boolean, and Std_Ulogic map to single bits
Mapping of other types will be made by the tool unless the ENUM_ENCODING attribute is used
Character type is suppored
Severity_level type is ignored
Integer type, Natural, and Positive are supported
A subtype with a descrete range should be used or the default 32 bit length will be synthesized
Physical types (e.g., time) are ignored
Floating point type is ignored - references to floating point objects can occur only within ignored constructs, e.g., After clauses, etc.
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29. Types (cont.) Array types are supported Record types are supported
Bounds must be specified directly or indirectly as static values of an integer type
Element subtype must denote a scalar type or a one dimensional vector of an enumerated type that denotes single bits
TYPE integer_array IS ARRAY(natural RANGE 7 DOWNTO 0) OF integer;
TYPE boolean_array IS ARRAY(integer RANGE <>) OF boolean;
...
SIGNAL bool_sig : boolean_array(-1 to 1);
Record types are supported
Access types are ignored
File types are ignored
File objects and file operations are not supported
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30. Attributes
The following predefined attributes for types are supported:
t’BASE
t’LEFT
t’RIGHT
t’HIGH
t’LOW
The following predefined attributes for array objects are supported:
a’LEFT
a’RIGHT
a’HIGH
a’LOW
a’RANGE
a’REVERSE_RANGE
a’LENGTH
The following predefined attributes for signals are supported
s’STABLE
s’EVENT
User defined attributes other than ENUM_ENCODING are NOT supported
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31. Concurrent Signal Assignment Statements
Simple concurrent signal assignment statements are supported
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY aoi_csa is
PORT(a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
y : OUT std_logic);
END aoi_csa;
ARCHITECTURE behavior OF aoi_csa IS
SIGNAL sig1,sig2 : std_logic;
BEGIN
sig1 <= a AND b;
sig2 <= c OR sig1;
y <= NOT sig2;
END behavior;
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY csa is
PORT(a : IN std_logic;
b : IN std_logic;
y : OUT std_logic);
END csa;
ARCHITECTURE behavior OF csa IS
BEGIN
y <= a NOR b;
END behavior;
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32. Conditional Signal Assignment Statements
Concurrent conditional signal assignment statements are supported - must end in else clause
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY mux2 is
PORT(a : IN std_logic;
b : IN std_logic;
sel : IN std_logic;
y : OUT std_logic);
END mux2;
ARCHITECTURE behavior OF mux2 IS
BEGIN
y <= a WHEN (sel = '0') ELSE
b WHEN (sel = '1') ELSE
'X';
END behavior;
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33. Selected Signal Assignment Statements
Concurrent selected signal assignment statements are supported
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY mux4 is
PORT(a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
sel : IN std_logic_vector(1 DOWNTO 0);
y : OUT std_logic);
END mux4;
ARCHITECTURE behavior OF mux4 IS
BEGIN
WITH sel SELECT
y <= a WHEN "00",
b WHEN "01",
c WHEN "10",
d WHEN "11",
'X' WHEN OTHERS;
END behavior;
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34. Operators
Generally, if the numeric_bit and numeric_std packages are supported, the operators within them are supported
Arithmetic operators - “abs”, “+”, “-”, “*”, “/”, “rem”, “mod”
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ENTITY divider is
PORT(divisor : IN unsigned(1 DOWNTO 0);
dividend : IN unsigned(1 DOWNTO 0);
quotient : OUT unsigned(1 DOWNTO 0));
END divider;
ARCHITECTURE behavior OF divider IS
BEGIN
quotient <= dividend / divisor;
END behavior;
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35. Operators (cont.)
Comparison operators - “>”, “<“, “<=“, “>=“, “=“, “/=“
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ENTITY compare is
PORT(a : IN unsigned(3 DOWNTO 0);
b : IN unsigned(3 DOWNTO 0);
aleb : OUT boolean);
END compare;
ARCHITECTURE behavior OF compare IS
BEGIN
aleb <= (a <= b);
END behavior;
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36. Operators (cont.)
Shift and conversion operators - “shift_left”, “shift_right”, “rotate_left”, “rotate_right”, “resize”, “to_integer”, “to_unsigned”
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ENTITY shift_4 is
PORT(a : IN unsigned(3 DOWNTO 0);
b : IN unsigned(1 DOWNTO 0);
y : OUT unsigned(3 DOWNTO 0));
END shift_4;
ARCHITECTURE behavior OF shift_4 IS
BEGIN
y <= shift_left(a,to_integer(b));
END behavior;
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37. Process Statements Process statements are supported
Postponed processes (or postponed concurrent signal assignment statements) are NOT supported
Process statement can have either a sensitivity list or a WAIT statement
Sensitivity list is ignored for synthesis (by most tools) - thus, to avoid simulation mismatches, all signals which appear on the RHS should be in the sensitivity list
Only one WAIT statement per process is allowed and it must be the first statement in the process after BEGIN
Only the WAIT UNTIL syntax of the WAIT statement is supported
WAIT UNTIL input1 = ‘1’;
WAIT UNTIL clock’EVENT and clock = ‘1’;
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38. Process Statements Example
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY aoi_process is
PORT(a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
y : OUT std_logic);
END aoi_process;
ARCHITECTURE behavior OF aoi_process IS
SIGNAL sig1 : std_logic;
BEGIN
comb : PROCESS(a,b,c,sig1)
sig1 <= a AND b;
y <= not(sig1 or c);
END PROCESS comb;
END behavior;
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39. Process Statements Incomplete Sensitivity List
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY aoi_process is
PORT(a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
y : OUT std_logic);
END aoi_process;
ARCHITECTURE behavior OF aoi_process IS
SIGNAL sig1 : std_logic;
BEGIN
comb : PROCESS(a,b,c)
sig1 <= a AND b;
y <= not(sig1 or c);
END PROCESS comb;
END behavior; a y b c
sig1 U a y b c
sig1
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40. Sequential Signal Assignment Statements
Various types of signal assignment statements inside a process statement (sequential signal assignment statements) are supported
IF statements
Case statements
Loop statement
Only For loops supported
Bounds must be specified as static values of an integer type
Exit and Next statements supported (without lables)
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41. Sequential IF Statements
IF statements are supported
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY xor_process is
PORT(a : IN std_logic;
b : IN std_logic;
y : OUT std_logic);
END xor_process;
ARCHITECTURE behavior OF xor_process IS
BEGIN
comb : PROCESS(a,b)
IF((a = '1' and b = '0') OR
(a = '0' and b = '1')) THEN
y <= '1';
ELSE
y <= '0';
END IF;
END PROCESS comb;
END behavior;
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42. Sequential Case Statements
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY mux4_process is
PORT(a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
sel : IN std_logic_vector(1 DOWNTO 0);
y : OUT std_logic);
END mux4_process;
ARCHITECTURE behavior OF mux4_process IS
BEGIN
comb : PROCESS(a,b,c,d,sel)
CASE sel IS
WHEN "00" => y <= a;
WHEN "01" => y <= b;
WHEN "10" => y <= c;
WHEN "11" => y <= d;
WHEN OTHERS => y <= 'X';
END CASE;
END PROCESS comb;
END behavior;
Case statements are supported
Choices which include metalogical values are never taken
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43. Sequential Loop Statements
Only For loops with integer range are supported
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY shift4 is
PORT(mode : IN std_logic;
shift_in : IN std_logic;
a : IN std_logic_vector(4 DOWNTO 1);
y : OUT std_logic_vector(4 DOWNTO 1);
shift_out : OUT std_logic);
END shift4;
ARCHITECTURE behavior OF shift4 IS
SIGNAL in_temp : std_logic_vector(5 DOWNTO 0);
SIGNAL out_temp : std_logic_vector(5 DOWNTO 1);
BEGIN
in_temp(0) <= shift_in;
in_temp(4 DOWNTO 1) <= a;
in_temp(5) <= '0';
comb : PROCESS(mode,in_temp,a)
FOR i IN 1 TO 5 LOOP
IF(mode = '0') THEN
out_temp(i) <= in_temp(i-1);
ELSE
out_temp(i) <= in_temp(i);
END IF;
END LOOP;
END PROCESS comb;
y <= out_temp(4 DOWNTO 1);
shift_out <= out_temp(5);
END behavior;
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44. Procedures and Functions
Procedures and Functions are supported - with limitations to allowed statement types
Procedures and functions may be in a package or in the declarative part of the architecture
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
PACKAGE logic_package IS
FUNCTION majority(in1, in2, in3 : std_logic) RETURN std_logic;
PROCEDURE decode(SIGNAL input : IN std_logic_vector(1 DOWNTO 0);
SIGNAL output : OUT std_logic_vector(3 DOWNTO 0));
END logic_package;
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45. Procedures and Functions (cont.)
PACKAGE BODY logic_package IS
FUNCTION majority(in1, in2, in3 : std_logic) RETURN std_logic IS
VARIABLE result : std_logic;
BEGIN
IF((in1 = '1' and in2 = '1') or (in2 = '1' and in3 = '1') or
(in1 = '1' and in3 = '1')) THEN
result := '1';
ELSIF((in1 = '0' and in2 = '0') or (in2 = '0' and in3 = '0') or
(in1 = '0' and in3 = '0')) THEN
result := '0';
ELSE
result := 'X';
END IF;
RETURN result;
END majority;
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46. Procedures and Functions (cont.)
PROCEDURE decode(SIGNAL input : IN std_logic_vector(1 DOWNTO 0);
SIGNAL output : OUT std_logic_vector(3 DOWNTO 0)) IS
BEGIN
CASE input IS
WHEN "00" =>
output <= "0001";
WHEN "01" =>
output <= "0010";
WHEN "10" =>
output <= "0100";
WHEN "11" =>
output <= "1000";
WHEN OTHERS =>
output <= "XXXX";
END CASE;
END decode;
END logic_package;
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47. Using Procedures and Functions
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.logic_package.all;
ENTITY voter IS
PORT(a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
y : OUT std_logic);
END voter;
ARCHITECTURE maj OF voter IS
BEGIN
y <= majority(a,b,c);
END maj;
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48. Using Procedures and Functions (cont.)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.logic_package.all;
ENTITY decoder IS
PORT(y : IN std_logic_vector(1 DOWNTO 0);
g : OUT std_logic_vector(3 DOWNTO 0));
END decoder;
ARCHITECTURE dec OF decoder IS
BEGIN
comb : PROCESS(y)
decode(y,g);
END PROCESS comb;
END dec;
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49. Tri-State Logic
Tri-state logic is infered when an object is assigned an IEEE Std value ‘Z’
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY tri_state4 is
PORT(enable : IN std_logic;
a : IN std_logic_vector(3 DOWNTO 0);
y : OUT std_logic_vector(3 DOWNTO 0));
END tri_state4;
ARCHITECTURE behavior OF tri_state4 IS
BEGIN
y <= a WHEN (enable = '1') ELSE
"ZZZZ";
END behavior;
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50. Use of Don’t Cares (‘X’s)
IEEE Std values of ‘X’ or ‘-’ can be used to specify “don’t care” conditions
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY not_xor is
PORT(a : IN std_logic;
b : IN std_logic;
y : OUT std_logic);
END not_xor;
ARCHITECTURE behavior OF not_xor IS
BEGIN
comb : PROCESS(a,b)
IF((a = '1' and b = '0') OR
(a = '0' and b = '1')) THEN
y <= '1';
ELSE
y <= 'X'; -- could also be ‘-’
END IF;
END PROCESS comb;
END behavior;
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51. After Clauses
Although not defined by the language, most simulator’s waveform windows do not show VHDL delta cycles adequately, if at all
Debugging large behavioral simulations before synthesis can be difficult if no delays are used - everything appears to happen simultaneously
List windows typically show delta cycles, but can be difficult to interpret
The solution is to put “dummy” delays in the behavioral descriptions using After clauses to “spread out” the events
After clauses are ignored for synhtesis
CONSTANT delay : TIME := 5 ns;
...
output <= input + 1 AFTER delay;
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52. Inferring Latches
If signals or variables are not assigned values in some conditional expressions of IF or Case statements, level-sensitive sequential logic might result
ARCHITECTURE behavior OF mux3_seq IS
BEGIN
comb : PROCESS(a,b,c,sel)
CASE sel IS
WHEN "00" => y <= a;
WHEN "01" => y <= b;
WHEN "10" => y <= c;
WHEN OTHERS => --empty
END CASE;
END PROCESS comb;
END behavior;
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY mux3_seq is
PORT(a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
sel : IN std_logic_vector(1 DOWNTO 0);
y : OUT std_logic);
END mux3_seq;
Note that most synthesis tools will issue a warning if latches are being inferred. These warnings need to be taken seriously!
Also, the proposed IEEE RTL Level synthesis standard allows values not to be assigned in all cases to variable and signals. However, some synhtesis tools will flag an error if this partial assignment is done with variables.
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53. Avioding Latches
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY mux3 is
PORT(a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
sel : IN std_logic_vector(1 DOWNTO 0);
y : OUT std_logic);
END mux3;
ARCHITECTURE behavior OF mux3 IS
BEGIN
comb : PROCESS(a,b,c,sel)
CASE sel IS
WHEN "00" => y <= a;
WHEN "01" => y <= b;
WHEN "10" => y <= c;
WHEN OTHERS => y <= 'X';
END CASE;
END PROCESS comb;
END behavior;
Assigning values of “don’t care” (‘X’ or ‘-’) in these cases can avoid this
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54. Problems to Avoid Inferring Latches in Complex Behaviors
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
ENTITY pc_comb IS
PORT(data_in : IN unsigned(3 DOWNTO 0);
cntrl : IN unsigned(1 DOWNTO 0);
data_out : OUT unsigned(3 DOWNTO 0));
END pc_comb;
ARCHITECTURE rtl OF pc_comb IS
SIGNAL pc : unsigned(3 DOWNTO 0);
BEGIN
one : PROCESS(dat_in, cntrl, pc)
CASE cntrl IS
WHEN "01" => pc <= (pc + "0001");
WHEN "10" => pc <= pc;
WHEN OTHERS => pc <= data_in;
END CASE;
END PROCESS one;
DATA_OUT <= PC;
END rtl;
This is not that complex a description, but the point is, it is much easier to infer latches in a complex behavioral description. For example, consider the description of a style ALU that has a four bit mode input and 16 logical and arithemetic modes. This might be coded as a large CASE statement. It is VERY important that the outputs be assigned values for ALL conditionls in the CASe statement or latches will be inferred as they are here.
There is NO hope of getting this machine to run correctly in a repeatable fashion across multiple implementations because of race conditions.
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55. Problems to Avoid Synthesizing Asynchronous State Machines!
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ENTITY pc_comb2 is
PORT(dat_in : IN unsigned(3 DOWNTO 0);
cntrl : IN std_logic;
data_out : OUT unsigned(3 DOWNTO 0));
END pc_comb2;
ARCHITECTURE rtl OF pc_comb2 IS
SIGNAL pc : unsigned(3 DOWNTO 0);
BEGIN
one : PROCESS(data_in, cntrl, pc)
CASE cntrl IS
WHEN '1' => pc <= (pc + "0001");
WHEN '0' => pc <= data_in;
WHEN OTHERS => pc <= "XXXX";
END CASE;
END PROCESS one;
dat_out <= pc;
END rtl;
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56. Level Sensitive D Latch
Use IF statement without Else clause
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY d_latch is
PORT(d : IN std_logic;
clk : IN std_logic;
q : INOUT std_logic;
qn : OUT std_logic);
END d_latch;
ARCHITECTURE behavior OF d_latch IS
BEGIN
seq : PROCESS(d,clk)
IF(clk = '1') THEN
q <= d;
END IF;
END PROCESS seq;
qn <= not q;
END behavior;
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57. Master-Slave D Latch (D Flip-Flop)
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY ms_latch is
PORT(d : IN std_logic;
clk : IN std_logic;
q : INOUT std_logic;
qn : OUT std_logic);
END ms_latch;
ARCHITECTURE behavior OF ms_latch IS
SIGNAL q_int : std_logic;
BEGIN
seq1 : PROCESS(d,clk)
IF(clk = '1') THEN
q_int <= d;
END IF;
END PROCESS seq1;
seq2 : PROCESS(q_int,clk)
IF(clk = '0') THEN
q <= q_int;
END PROCESS seq2;
qn <= not q;
END behavior;
Optimize
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58. Edge Sensitive D Flip-Flop
Clocks must be of BIT or STD_LOGIC type - metalogic values not allowed
Rising_edge() and Falling_edge() functions can be used to specify clock edge
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY d_ff is
PORT(d : IN std_logic;
clk : IN std_logic;
q : INOUT std_logic;
qn : OUT std_logic);
END d_ff;
ARCHITECTURE behavior OF d_ff IS
BEGIN
seq : PROCESS(clk)
IF(rising_edge(clk)) THEN
q <= d;
END IF;
END PROCESS seq;
qn <= not q;
END behavior;
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59. Edge Sensitive D Flip-Flop (cont.)
Wait statement can be used
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY d_ff_w is
PORT(d : IN std_logic;
clk : IN std_logic;
q : INOUT std_logic;
qn : OUT std_logic);
END d_ff_w;
ARCHITECTURE behavior OF d_ff_w IS
BEGIN
seq : PROCESS
WAIT UNTIL rising_edge(clk);
q <= d;
END PROCESS seq;
qn <= not q;
END behavior;
ARCHITECTURE behavior OF d_ff_w IS
BEGIN
seq : PROCESS
WAIT UNTIL clk = ‘1’;
q <= d;
END PROCESS seq;
qn <= not q;
END behavior;
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60. Edge Sensitive Flip-Flops
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY d_ff_pc is
PORT(d : IN std_logic;
clk : IN std_logic;
pre : IN std_logic;
clr : IN std_logic;
q : INOUT std_logic;
qn : OUT std_logic);
END d_ff_pc;
ARCHITECTURE behavior OF d_ff_pc IS
BEGIN
seq : PROCESS(clk,pre,clr)
IF(pre = '0') THEN
q <= '1';
ELSIF(clr = '0') THEN
q <= '0';
ELSIF(rising_edge(clk)) THEN
q <= d;
END IF;
END PROCESS seq;
qn <= not q;
END behavior;
Preset and clear functions can be added
Asynchronous with respect to the clock
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61. Edge Sensitive Flip-Flops
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY d_ff_spc is
PORT(d : IN std_logic;
clk : IN std_logic;
pre : IN std_logic;
clr : IN std_logic;
q : INOUT std_logic;
qn : OUT std_logic);
END d_ff_spc;
ARCHITECTURE behavior OF d_ff_spc IS
BEGIN
seq : PROCESS(clk)
IF(rising_edge(clk)) THEN
IF(pre = '0') THEN
q <= '1';
ELSIF(clr = '0') THEN
q <= '0';
ELSE
q <= d;
END IF;
END PROCESS seq;
qn <= not q;
END behavior;
Preset and clear functions can be added
Synchronous with respect to the clock
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62. Finite State Machine Synthesis
State machines can be modeled as a combinational portion and a sequential portion
Both Mealy and Moore type state machines can be described
Most synthesis tools employ special algorithms to minimize state machines - thus standard procedures must be used to enable the tool to recognize the state machine
Huffman FSM Model
Primary
Inputs
Combinational
Logic
Primary
Outputs
Present
State
Next
State
Memory
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63. Mealy and Moore State Machine Models
A state machine has three basic parts
Next State Logic
Output Logic
Memory
The most straight-forward way to code a synthesizable state machine is to use one process per function
Mealy Machine Model
Moore Machine Model
Primary
Inputs
Output
Combinational
Logic
Primary
Outputs
Primary
Inputs
Output
Combinational
Logic
Primary
Outputs
Next State
Combinational
Logic
Next State
Combinational
Logic
Present
State
Next
State
Present
State
Next
State
Memory
Memory
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