1. State Reduction and State Assignment

2. Elimination of Redundant States
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ECE Digital System Design

3. Elimination of Redundant States
In Unit 14, we were careful to avoid introducing unnecessary states when setting up a state graph or table. We will now approach the problem of deriving the state graph somewhat differently. When first setting up the state table, we will not be overly concerned with inclusion of extra states, and when the table is complete, we will eliminate any redundant states.
We will rework Example 1 in Section 14.3 using excess states, and then eliminate the excess states.
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ECE Digital System Design

4. Example: Sequence Detector
A sequential circuit has one input (X) and one output (Z). The circuit examines groups of four consecutive inputs and produces an output Z = 1 if the input sequence 0101 or 1001 occurs. The circuit resets after every four inputs. Find a Mealy state graph. A typical input and output sequence is:
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ECE Digital System Design

5. Example: Sequence Detector
State Table
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ECE Digital System Design

6. Example: Sequence Detector
Since states H and I have the same next states and the same outputs, there is no way of telling states H and I apart.
We can replace I with H.
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ECE Digital System Design

7. Example: Sequence Detector
Reduced State Table
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ECE Digital System Design

8. Example: Sequence Detector
Reduced State Graph
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ECE Digital System Design

10. Determination of Equivalent States
a ≡ b iff
d ≡ f and c ≡ h
a ≡ d iff
a ≡ d and c ≡ e
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ECE Digital System Design

11. ECE 331 - Digital System Design
Implication Chart
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ECE Digital System Design

12. ECE 331 - Digital System Design
Implication Chart
After first pass.
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ECE Digital System Design

13. ECE 331 - Digital System Design
Implication Chart
After second pass.
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ECE Digital System Design

16. Implication Table Method
3. Go through the table square-by-square. If square i-j contains the implied pair m-n, and square m-n contains an X, then i j, and an X should be placed in square i-j.
4. If any X’s were added in step 3, repeat step 3 until no more X’s are added.
5. For each square i-j which does not contain an X, i ≡ j.
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ECE Digital System Design

17. Future site of another example.
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ECE Digital System Design

18. Derivation of FF Input Equations
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ECE Digital System Design

19. Derivation of FF Input Equations
After the number of states in a state table has been reduced, the following procedure can be used to derive the flip-flop input equations:
Assign flip-flop state values to correspond to the states in the reduced table.
Construct a transition table which gives the next states of the flip-flops as a function of the present states and inputs.
Derive the next-state maps from the transition table.
Find flip-flop input maps from the next-state maps using the techniques developed in Unit 12 and find the flip-flop input equations from the maps.
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ECE Digital System Design

20. Example #1: FF Input Equations
Assign flip-flop state values to correspond to the states in the reduced table.
Construct a transition table which gives the next states of the flip-flops as a function of the present states and inputs.
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ECE Digital System Design

21. Example #1: FF Input Equations
3. Derive the next-state maps from the transition table.
D FF Characteristic Equation:
Q+ = D
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ECE Digital System Design

22. Example #1: FF Input Equations
4. Derive the flip-flop input maps from the next-state maps; determine the flip-flop input equations from the FF input maps.
JK Excitation Table Q Q+ J K x 1
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23. Example #2: FF Input Equations
Assign flip-flop state values to correspond to the states in the reduced table.
Construct a transition table which gives the next states of the flip-flops as a function of the present states and inputs.
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ECE Digital System Design

24. Example #2: FF Input Equations
3. Derive the next-state maps from the transition table.
D FF Characteristic Equation:
Q+ = D
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25. Example #2: FF Input Equations
4. Derive the flip-flop input maps from the next-state maps; determine the flip-flop input equations from the FF input maps.
SR Excitation Table Q Q+ S R x 1
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26. ECE 331 - Digital System Design
State Assignment
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ECE Digital System Design

27. ECE 331 - Digital System Design
State Assignments
After the number of states in a state table has been reduced, the next step in realizing the transition table (aka. state- assigned table) is to assign flip-flop states (i.e. binary values) to correspond to the states in the state table.
The cost of the logic required to realize a sequential circuit is strongly dependent on the way this state assignment is made.
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ECE Digital System Design

28. ECE 331 - Digital System Design
State Assignments
Given a sequential circuit with three states and two flip-flops (A and B), there are 4 × 3 × 2 = 24 possible state assignments for the three states.
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ECE Digital System Design

29. ECE 331 - Digital System Design
State Assignments
When realizing a three-state sequential circuit with symmetrical flip-flops (i.e. JK or SR), it is only necessary to try three different states to be assured of a minimum cost realization.
Similarly, only three different assignments must be tried for four states.
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ECE Digital System Design

30. ECE 331 - Digital System Design
State Assignments
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ECE Digital System Design

31. Guidelines for State Assignment
Trying all nonequivalent state assignments is not practical in most cases. The following guidelines are useful in making assignments which will place 1’s (or 0's) together in the next-state maps:
States which have the same next state for a given input should be given adjacent assignments.
States which are the next states of the same state should be given adjacent assignments.
States which have the same output for a given input should be given adjacent assignments.
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ECE Digital System Design

32. Example: Selecting an Assignment
States which have the same next state for a given input should be given adjacent assignments.
States which are the next states of the same state should be given adjacent assignments.
States which have the same output for a given input should be given adjacent assignments.
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ECE Digital System Design

33. Example: Selecting an Assignment
Based on the State Assignment Guidelines:
1. (b, d) (c, f) (b, e)
2. (a, c) (d, f) (b, d) (b, f) (c, e)
3. (a, c) (b, d) (e, f)
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ECE Digital System Design

34. Example: Selecting an Assignment
Resulting Transition Table:
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ECE Digital System Design

35. Example: Selecting an Assignment
Derivation of FF input equations from next-state maps:
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ECE Digital System Design

36. One-Hot State Assignment
Sometimes reducing the number of flip-flops used is not as important as reducing the logic feeding into the flip-flops. Using a one-hot state assignment may help accomplish this.
The one-hot assignment uses one flip-flop for each state, so a state machine with N states requires N flip-flops. Exactly one of the flip-flops is set to one in each state.
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ECE Digital System Design

37. Example: State Assignments
For a four-state FSM, three possible state assignments are:
State
Binary
Gray-code
One-hot S0 00
0001 S1 01
0010 S2 10 11
0100 S3
1000
# of FF 2 4
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ECE Digital System Design

38. ECE 331 - Digital System Design
Questions?
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ECE Digital System Design