EECS150 Spring 2007 Lab Lecture #9 Neil Warren

EECS150 Spring 2007 Lab Lecture #9 Neil Warren
Wireless Transceiver EECS150 Spring 2007 Lab Lecture #9 Neil Warren 9/21/2018 EECS150 Spring Neil Warren

Transceiver Overview (1)
3rd party chip mounted on expansion board. Uses a PCB antenna. Take a look! IEEE standard support. Zigbee ready. Transmits on unlicensed 2.4 GHz spectrum. 16 communication channels. Overlaps with Wi-Fi. 250 kbps maximum data rate. Configure, send, receive, and issue commands to chip over SPI to CC2420 registers. 9/21/2018 EECS150 Spring Neil Warren

33 configuration registers. We change 3 of them. 15 command strobe registers. We issue 6 of them. These change the state of the CC2420 internal FSM. 128-byte RX FIFO & 128-byte TX FIFO Accessed via 2 additional registers. Also accessible as RAM (i.e. by addressing). Only for debugging! Don’t do this unless you’re a masochist 9/21/2018 EECS150 Spring Neil Warren

You will need to read the data sheet to learn more about how the CC2420 works in more detail than what we can fit in the Spec. MDPU Status Registers (more info.) Commands (more info.) Internal state machine (very helpful!!) 9/21/2018 EECS150 Spring Neil Warren

EECS150 Spring 2007 - Neil Warren
CC2420 Inputs & Outputs Single bit status signals. High level transceiver operation information. Initialization signals. Drive signals once and forget about it. SPI interface. Interface to rest of chip via CC2420 registers. Send, receive, configuration, detailed status. FPGA VREG_EN RF_RESET_ 9/21/2018 EECS150 Spring Neil Warren

Single Bit Status Indicators
FIFO – Goes high when there’s received data in RX FIFO. FIFOP – Goes high when # bytes received exceeds set threshold. CCA – Indicates that the transmission medium (air) is clear. Only valid after 8 symbol periods in RX mode. SFD – Goes high after SFD is transmitted & low after packet completely sent. 9/21/2018 EECS150 Spring Neil Warren

SPI Interface Serial interface with 4 wires: SClk – Clock signal you generate. CS_ – Active-low chip select. SI – Output to the CC2420. SO – Input from the CC2420. Interface to the chip! Initialization, configuration, TX, RX, detailed status. Luckily for you, it’s provided as a black box. 9/21/2018 EECS150 Spring Neil Warren

CC2420-specific SPI (1): First Byte
Sent First  Bit Position  Sent Later 7 6 5:0 1 = RAM access (not used) 0 = register access 1 = read 0 = write Address of register. Refer to p. 60 of the datasheet. First byte always has above format. Bit 7 – Set to 0 for register access. Bit 6 – Read/write control. Bits 5:0 – Address of register. P. 60 of datasheet. Followed by data specific to register being accessed. 9/21/2018 EECS150 Spring Neil Warren

CC2420-specific SPI (2): Writing to Configuration Reg.
Sent First  Byte Number  Sent Later 1 2 - 3 Sent on SI address byte, described above 16 bits of data to be written to register Received on SO status byte 16’bX First byte followed by 2 bytes of configuration data. Data on SO invalid here. Transceiver replies when first byte is sent out with status byte. True for all SPI accesses. Not necessary to inspect, but can be helpful for debugging! 9/21/2018 EECS150 Spring Neil Warren

CC2420-specific SPI (3): Issuing Command Strobes
Byte Number 1 Sent on SI address byte, described above Received on SO status byte One byte only. Nothing follows. Address sent indicates the command strobe being issued. Note that 0x00 is NO OP. This is useful for explicitly retrieving status byte. 9/21/2018 EECS150 Spring Neil Warren

CC2420-specific SPI (4): Saving to TX FIFO
Sent First  Byte Number  Sent Later 1 2 to n Sent on SI address byte, described above data bytes to be transmitted Received on SO status byte After first byte, send n bytes of data to transmit over wireless. SPI session only ends when CS_ is pulled high. CC2420 replies with a new status byte with each byte that’s saved to FIFO. 9/21/2018 EECS150 Spring Neil Warren

CC2420-specific SPI (5): Receive from RX FIFO
Received First  Byte Number  Received Later 1 2 to n Sent on SI address byte, described above 8’bX Received on SO status byte data from the RX FIFO After first byte, send a n bytes of “don’t care” in order to receive data. During first byte, CC2420 replies with status. Subsequent bytes are data saved in FIFO. Must be careful not to request data from empty FIFO! SPI session only ends when CS_ is pulled high. Reading from a configuration register is the same. 9/21/2018 EECS150 Spring Neil Warren

Configuration Registers
Address Bit(s) of Interest Purpose MDMCTRL0 0x11 11 Turn off automatic address recognition. You must set bit 11 to 1’b0. FSCTRL 0x18 9:0 Channel changing. IOCFG0 0x1C 6:0 Changes the threshold of number of bytes in RX FIFO before FIFOP goes high. Defaults to 64. You may want to change this value. 9/21/2018 EECS150 Spring Neil Warren

Command Strobe Registers
Address Purpose SNOP 0x00 No operation. SXOSCON 0x01 Turns on the crystal oscillator and will be used as part of the initialization process. SRXON 0x03 Moves the CC2420 into the receive state and will be used as part of the initialization and channel changing process. STXON 0x04 Instructs the CC2420 to transmit the data contained in the TX FIFO. SRFOFF 0x06 Turns off RX/TX and frequency synthesizer and will be used as part of channel changing. SFLUSHRX 0x08 Flushes the RX FIFO. This command will be used a lot! 9/21/2018 EECS150 Spring Neil Warren

TX/RX FIFO Registers Register Address Purpose TXFIFO 0x3E For saving bytes to transmit into the TX FIFO. You must not write data to the FIFO while a transmission is in progress. RXFIFO 0x3F For retrieving bytes from the RX FIFO. 9/21/2018 EECS150 Spring Neil Warren

Initialization 9/21/2018 EECS150 Spring Neil Warren

Transmit 9/21/2018 EECS150 Spring Neil Warren

Transmit(2) CC2420 needs 12 symbol periods to move into RX_SFD_SEARCH state after transmit done or SRXON. 1 symbol period = 16 us. Without enforcing wait, aggressive user of your Transceiver module will cause CC2420 to never receive data from air. 9/21/2018 EECS150 Spring Neil Warren

CCA If you don’t follow CCA we will dock MAJOR points If CCA isn’t high, you must wait a RANDOM AMOUNT OF TIME CCA may also not go high if you have buffer overflow. FIFOP & !FIFO 9/21/2018 EECS150 Spring Neil Warren

Receive (1) 9/21/2018 EECS150 Spring Neil Warren

Receive (2) You must be able to receive while the random CCA wait time is expiring! Packets are only received after CC2420 has spent 12 symbol periods in receive mode. There must be wait time between transmissions. Allows the transceiver to look for and receive data. 9/21/2018 EECS150 Spring Neil Warren

Receive(3) Refers to 2 things: CC2420 is constantly receiving and saving data into RX FIFO as long as it’s not transmitting. Look at CC2420 internal FSM on p. 43. You have to “receive” data from RX FIFO, filter it, then save wanted data into SPIFifo. 9/21/2018 EECS150 Spring Neil Warren

Design Structure (2) Transceiver – Highest level block. 32-bit input/output, channel changing, addressing. SPI Abstraction – Takes care of details of CC2420 SPI interface. Arbitrates between TX/RX. SPI (provided) – Handles details of interface timing. 9/21/2018 EECS150 Spring Neil Warren

Packet Format MPDU Preamble SFD Length Source Dest. Payload Frame Check Sequence (CRC) 4 bytes 1 byte 12 bytes 2 bytes 0x00 0x7A ??? Design Review Question! sender’s addr. recipient’s addr. or 0xFF For broadcast data On transmit, 0x00. On receive, bit 7 of the 2nd byte is 1 when CRC ok, 0 otherwise. On transmit, only fill TX FIFO starting with length byte. Preamble & SFD automatically appended. Transmit all zeros for CRC. CC2420 will replace. 9/21/2018 EECS150 Spring Neil Warren

Channel & Addresses There are 16 channels. Your group will be assigned a channel. You must be able to change channels without reset! DO NOT USE ANOTHER CHANNEL BESIDES YOUR OWN This is a big class and we need to be able to partition the signal space! Address are 8-bits wide  256 addresses. Zero is unused. 0xFF is reserved for broadcast. 9/21/2018 EECS150 Spring Neil Warren

Interference & Debugging
Roughly 2-3 groups per channel. Each group in a particular lab has distinct channel. Can also pick up data on neighboring channel. Very first goal is robust channel changing during initialization. Can pick up packets sometimes. Your module must recover gracefully. Your project interferes with Wi-Fi & vice versa. 9/21/2018 EECS150 Spring Neil Warren

Handshaking: InRequest/Invalid
SPI uses a variation of this. You may want to use this internally. 9/21/2018 EECS150 Spring Neil Warren

Handshaking: Ready/Start
Transceiver uses this interface for input & output. 9/21/2018 EECS150 Spring Neil Warren

Debugging Tools Chipscope! We will be releasing some debugging utilities. Packet sniffer. Packet counter (The TA Solution does this) 9/21/2018 EECS150 Spring Neil Warren

Get Started! READ THE DATASHEET Obey our CCA rules 9/21/2018 EECS150 Spring Neil Warren

Danger! Danger! Don’t become complacent because you’ve *been* finishing checkpoints early Expect each checkpoint to be at least twice as difficult as the last. 1>>2>>>>3>>>>>>>>4! Get started early and get ahead. 9/21/2018 EECS150 Spring Neil Warren

EECS150 Spring 2007 Lab Lecture #9 Neil Warren

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EECS150 Spring 2007 Lab Lecture #9 Neil Warren

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