1. University of California Los Angeles
ALCT and TMB Status
Martin von der Mey
Jay Hauser
University of California Los Angeles
Mezzanine board production status
ALCT384 production status
ALCT672 and ALCT288 status
TMB prototype status
TMB future plans
Electronics integration at UC FAST site

2. Power, computer connectors
ALCT384 Boards
Power, computer connectors
80 MHz SCSI outputs
(to Trigger Motherboard)
Xilinx Mezz. board
24 Input signal connectors
Delay/ buffer ASICs,
2:1 bus multiplexors (other side)
Analog section:
test pulse generator, AFEB power,
ADCs, DACs
(other side)
Spartan XL

3. Mezzanine Board Status
All FPGAs were purchased.
462 XCV600E.
112 XCV1000E.
232 mezzanine boards were initially produced and assembled (120 XCV600E, 112 XCV1000E).
Additional order (230 XCV600E) of printed circuit boards received.
Problems with Xilinx Eproms. Some load but can’t verify (fail at address 0x0). Problem only with ISE (impact) and not with Foundation software. Xilinx changed production for them.
New 175 Mezz. Boards assembled. 100 already tested.(29 bad ones).
16 had problems with Eproms (shorts).
10 don’t verify (strange since pre tested).
3 not even load (TDO problem->reassemble).

4. ALCT Production Testing
Using 3 stations.
2 for testing.
1 for fixing.
2 shifts per day
Crew of 4 students testing.
2 students helping Valeri Iatsura with fixing.
Update database.

5. Testing Board

6. Problems Encountered Most frequent problem:
Delay chips have shorts.
Some replaced
Shorts at bus multiplexer
Seldom problem with delay chips after burn-in
Few problems with Slow Control Eprom. Had to replace them.

7. ALCT384 Boards Order of 250 boards sent for assembly
158 ALCT384 boards were received so far.
142 fully tested before and after 2 day x 70oc burn-in.
6 boards require repair.
10 boards still need to be tested.
Enough boards for shipping to FAST sites.
45 shipped to UCLA and UFL FAST sites
already.
Have parts for all boards including -672, -288
varieties.

8. ALCT-384 Production

9. ALCT-672 and ALCT–288 Assembly of 6 boards of each type is complete
ALCT-672: 3 to PNPI, 1 at UF, 1 FNAL, 1 at UCLA
ALCT-288: 3 to IHEP, 1 at UF, 2 at UCLA
Boards fully tested and no problems were found
First batch of 123 out of 130 ALCT-672 PC boards delivered
Sent 22 ALCT-672 for assembling
Should we do a batch of the ALCT-288 (22 or more)?
Waiting for chamber tests before assembling additional boards (?)

10. ALCT-672, ALCT-288
ALCT-672
ALCT-288

11. Problems found (FAST) 5 problem boards, all fixed:
ALCT loaded with wrong FPGA firmware.
ALCT was sending wrong standby patterns.
ALCT was noisy. One of the test pulse outputs was always enabled.
ALCT displayed wrong temperature and current. Problem with ADCs.
Connectors improperly soldered.
Test suite was updated to eliminate
future problems.
Also, sensitivity to very large external
electromagnetic noise (arc welding).
Used Faraday generator to test this.

12. Trigger Motherboard (TMB)
Input
connectors
From ALCT
Main FPGA
(on back)
XILINX XCV1000E
Mezzanine board
From 5 CFEB’s
Generates Cathode LCT trigger with input from CFEB (comparator)
Matches ALCT and CLCT; sends trigger primitive info via MPC to Lev-1 muon trigger, sends anode and cathode hits to DMB.

13. TMB Integration at UCLA FAST Site in May
Full set of peripheral crate electronics:
TMB with DMB, CCB
DDU readout through Gbit Ethernet to Linux PC
Also full set of AFEB, CFEB, ME2/2 chamber
Debugged DAQ readout
Timed in DAQ system
Debugged trigger modes
Developed software libraries for downloading FPGAs and talking to boards via VME

14. TMB Prototype Status 18 boards assembled and working.
Some assembly problems with connectors.
PHOS4 delay ASIC write-only setting work-around (shadow register).
PHOS4 delay ASIC unreliable power-on reset sequence fixed.
PHOS4 problems only in combination with CCB PHOS4 delay chips.
Full set of bench tests.
Testing board built to check inputs and outputs (VME backplane).
Next set of tests at UCLA with OSU under discussion:
Integration of the whole system
DDU readout (TTCrx?)
Multi chamber and multi crate readout
Full set of trigger patterns
High-rate tests

15. Current TMB Modes Source Delay Ext Description CLCT VPF No N
Type
Source
Delay
Ext
Description
CLCT VPF No N
Cathode LCT Pattern Trigger, this is the normal trigger mode 1
ALCT VPF
Adj Y
ALCT Trigger acting as Scintillator 2
ADB Test Pulse
Anode Test Pulse Trigger 3
DMB Ext Trig
DMB Calibration Trigger 4
CLCT Ext Trig
FAST Site Scintillator Trigger 5
ALCT Ext Trig
ALCT External trigger, force TMB readout if ALCT VPF absent 6
VME Ext Trig
VME External trigger, for self-test

16. TMB Future Plans (Hardware)
Real peripheral crates will require a transition module in back to receive signals from ALCT and RPC cables.
Virtex-II mezzanine card may be produced to replace Virtex-E.
Producing small PC board for PHOS4 replacement.

17. PHOS4 Replacement New Delay chips
TMB uses PHOS4 chips for adjusting 10 clock delays (CFEBs, ALCT, DMB and RPC).
Trying out Data Delay Devices (3D3444).
Each has 4 channels  PHOS4 5 channels => 3 chips necessary to replace 2 PHOS4 chips.
They have (16x2.0ns) and (16x1.5ns).
First test (2.0ns) duty cycle 68/32 for data sent from CFEB to TMB
New Delay chips

18. TMB Firmware Plans Top priorities, mainly for FAST sites:
Change the key layer from 3 to 4 for software reasons (ORCA).
Add di-strip and multiple patterns.
Di-strip patterns greatly increase (x4 to x16) the flux of cosmic ray CLCTs at the FAST sites.
Multiple patterns are included in the ORCA simulation.
First approach lead to a big FPGA (XC2V4000).
New will probably fit in the old XCV1000E.
Add DAQ multi-buffer handling capability.
Add RPC coincidence logic.
Replace PHOS4 chips. New firmware necessary.

19. TMB Patterns (First Try)
Ly0 _x__
Ly1 _x__
Ly2 _x__
Ly3 _x__
Ly4 __x_
Ly5 __x_
Ly0 _x__
Ly1 _x__
Ly2 _x__
Ly3 _x__
Ly4 _x__
Ly5 _x__
Ly0 x___
Ly1 x___
Ly2 xx__
Ly3 _x__
Ly4 _x__
Ly5 _x__
Ly0 __x_
Ly1 __x_
Ly2 _xx_
Ly3 _x__
Ly4 _x__
Ly5 _x__
Ly0 _x__
Ly1 _x__
Ly2 _x__
Ly3 _x__
Ly4 x___
Ly5 x___
Ly0 x___
Ly1 x___
Ly2 xx__
Ly3 _x__
Ly4 _xx_
Ly5 __x_
Ly0 __x_
Ly1 __x_
Ly2 _xx_
Ly3 _x__
Ly4 xx__
Ly5 x___
Use angle to decide priority of muons
Didn’t fit XCV1000E
XC2V4000 necessary

20. TMB Patterns Ly0 xxx_ Ly1 xxx_ Ly2 xxx_ Ly3 _x__ Ly4 xxx_ Ly5 xxx_
New TMB firmware:
Ly0 xxx_
Ly1 xxx_
Ly2 xxx_
Ly3 _x__
Ly4 xxx_
Ly5 xxx_
Hits ordered by priority
Programmable for each ½-cell
Bending angle look-up after selection
Di-strip envelopes included
Fits XCV1000E

21. New CSC Event Display Decode DDU information
Correlate CLCT & ALCT information
Check TMB information
See Brian Mohrs talk

22. Conclusions ALCT production in excellent shape.
Production of ALCT-672,-288.
Testing working fine. Implemented feedback from FAST site.
TMB prototypes in good shape.
Few minor changes to do to firmware and hardware of the TMB.
Testing PHOS4 replacement and new patterns.
New tests on the way with OSU toward full integration of the system.