1. Instructor: Dr. Phillip Jones
CPRE 583 Reconfigurable Computing Lecture 8: Fri 10/30/2009 (System Architectures)
Instructor: Dr. Phillip Jones
Reconfigurable Computing Laboratory
Iowa State University
Ames, Iowa, USA

2. Overview
Class Projects
Common System Architectures

3. Project Grading Breakdown
60% Final Project Demo
30% Final Project Report
30% of your project report grade will come from your 5 project updates. Friday’s midnight
10% Final Project Presentation

4. Project Update The current state of your project write up
Even in the early stages of the project you should be able to write a rough draft of the Introduction and Motivation section
The current state of your Final Presentation
What things are work & not working
What roadblocks are you running into

5. What you should learn
Introduction to common System Architectures

6. Outline
System Architectures
Why are they useful?
Examples

7. References Reconfigurable Computing (2008) [1]
Chapter 5: Compute Models and System Architectures
Scott Hauck, Andre DeHon

8. System Architectures
Compute Models: Help express the parallelism of an application
System Architecture: How to organize application implementation

9. Efficient Application Implementation
Compute model and system architecture should work together
Both are a function of
The nature of the application
Required resources
Required performance
The nature of the target platform
Resources available

10. Efficient Application Implementation
(Image Processing)
Platform 1
(Vector Processor)
Platform 2
(FPGA)

11. Efficient Application Implementation
(Image Processing)
Compute Model
System Architecture
Platform 1
(Vector Processor)
Platform 2
(FPGA)

12. Efficient Application Implementation
(Image Processing)
Compute Model
System Architecture
Platform 1
(Vector Processor)
Platform 2
(FPGA)

13. Efficient Application Implementation
(Image Processing)
Data Flow
Compute Model
Streaming Data Flow
System Architecture
Platform 1
(Vector Processor)
Platform 2
(FPGA)

14. Efficient Application Implementation
(Image Processing)
Data Flow
Compute Model
Streaming Data Flow
System Architecture
Platform 1
(Vector Processor)
Platform 2
(FPGA)

15. Efficient Application Implementation
(Image Processing)
Compute Model
System Architecture
Platform 1
(Vector Processor)
Platform 2
(FPGA)

16. Efficient Application Implementation
(Image Processing)
Data Parallel
Compute Model
Vector
System Architecture
Platform 1
(Vector Processor)
Platform 2
(FPGA)

17. Efficient Application Implementation
(Image Processing)
Data Flow
Compute Model
Streaming Data Flow
System Architecture
Platform 1
(Vector Processor)
Platform 2
(FPGA)

18. Efficient Application Implementation
(Image Processing)
Data Flow
Compute Model
Streaming Data Flow
System Architecture
Platform 1
(Vector Processor)
Platform 2
(FPGA)

19. Implementing Streaming Dataflow
Data presence
variable length connections between operators
data rates vary between operator implementations
data rates varying between operators
Datapath sharing
not enough spatial resources to host entire graph
balanced use of resources (e.g. operators)
cyclic dependencies impacting efficiency
Interconnect sharing
Interconnects are becoming difficult to route
Links between operators infrequently used
High variability in operator data rates
Streaming coprocessor
Extreme resource constraints

20. Data Presence X X +

21. Data Presence X X
data_ready
data_ready +
data_ready

22. Data Presence X X
FIFO
FIFO
data_ready
data_ready +
FIFO
data_ready

23. Data Presence X X stall stall FIFO FIFO data_ready data_ready + FIFO

24. Data Presence Flow control: Term typical used in networking X X stall
FIFO
FIFO
data_ready
data_ready +
FIFO
stall
data_ready
Flow control: Term typical used in networking

25. Data Presence Flow control: Term typical used in networking
Increase flexibility of how application can be implemented X X
stall
stall
FIFO
FIFO
data_ready
data_ready +
FIFO
stall
data_ready
Flow control: Term typical used in networking

26. Implementing Streaming Dataflow
Data presence
variable length connections between operators
data rates vary between operator implementations
data rates varying between operators
Datapath sharing
not enough spatial resources to host entire graph
balanced use of resources (e.g. operators)
cyclic dependencies impacting efficiency
Interconnect sharing
Interconnects are becoming difficult to route
Links between operators infrequently used
High variability in operator data rates
Streaming coprocessor
Extreme resource constraints

27. Datapath Sharing X X +

28. Datapath Sharing
Platform may only have one multiplier X X +

29. Datapath Sharing
Platform may only have one multiplier X +

30. Datapath Sharing
Platform may only have one multiplier
REG X
REG +

31. Datapath Sharing
Platform may only have one multiplier
REG X
FSM
REG +

32. Datapath Sharing Platform may only have one multiplier
REG X
FSM
REG +
Important to keep track of were data is coming!!

33. Implementing Streaming Dataflow
Data presence
variable length connections between operators
data rates vary between operator implementations
data rates varying between operators
Datapath sharing
not enough spatial resources to host entire graph
balanced use of resources (e.g. operators)
cyclic dependencies impacting efficiency
Interconnect sharing
Interconnects are becoming difficult to route
Links between operators infrequently used
High variability in operator data rates
Streaming coprocessor
Extreme resource constraints

34. Interconnect sharing X X +

35. Interconnect sharing
Need more efficient use of interconnect X X +

36. Interconnect sharing
Need more efficient use of interconnect X X +

37. Interconnect sharing
Need more efficient use of interconnect X X
FSM +

38. Implementing Streaming Dataflow
Data presence
variable length connections between operators
data rates vary between operator implementations
data rates varying between operators
Datapath sharing
not enough spatial resources to host entire graph
balanced use of resources (e.g. operators)
cyclic dependencies impacting efficiency
Interconnect sharing
Interconnects are becoming difficult to route
Links between operators infrequently used
High variability in operator data rates
Streaming coprocessor
Extreme resource constraints

39. Streaming coprocessor

40. Sequential Control
Typically thought of in the context of sequential programming on a processor (e.g. C, Java programming)
Key to organizing synchronizing and control over highly parallel operations
Time multiplexing resources: when task to too large for computing fabric
Increasing data path utilization

41. Sequential Control X + A B C

42. Sequential Control X + A B C
A*x2 + B*x + C

43. Sequential Control X + A B C C A B X X +
A*x2 + B*x + C
A*x2 + B*x + C

44. Finite State Machine with Datapath (FSMD)B X X +
A*x2 + B*x + C

45. Finite State Machine with Datapath (FSMD)B X
FSM X +
A*x2 + B*x + C

46. Sequential Control: Types
Finite State Machine with Datapath (FSMD)
Very Long Instruction Word (VLIW) data path control
Processor
Instruction augmentation
Phased reconfiguration manager
Worker farm

47. Very Long Instruction Word (VLIW) Datapath Control

48. Processor

49. Instruction Augmentation

50. Phased Configuration Manager

51. Worker Farm

52. Bulk Synchronous Parallelism

53. Data Parallel Single Program Multiple Data
Single Instruction Multiple Data (SIMD)
Vector
Vector Coprocessor

54. Data Parallel

55. Data Parallel

56. Data Parallel

57. Data Parallel

58. Cellular Automata

59. Multi-threaded

60. Next Lecture
Evolvable Hardware (Chapter 33)

61. Slides in Progress
Need to revise this lecture with figures, and useful animations
Add some non-FPGA systems, maybe not since GARP, and PipeRench were discussed in last lecture. Perhaps just mention again
Main reason other archs are not used is economy of scales. Lots of FPGAs are manufacture, thus lowing cost and enable the use of state of the art fab technology (given high performance