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Low Latency Analytics HPC Clusters
Devashish Paul Dir Strategic Marketing IDT
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Agenda OCP HPC Project Overviews Heterogeneous Computing
RapidIO Low Latency Interconnect Technology Computing and Low Latency Switching Platforms for OCP CERN Use Case
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Mixed-signal application-specific solutions
IDT Company Overview Founded 1980 Workforce Approximately 1,800 employees Headquarters San Jose, California #1 Serial Switching – 100% 4G Infrastructure with RapidIO #1 Memory Interface – Industry Leader DDR4 #1 Silicon Timing Devices – Broadest Portfolio 800+ Issued and Pending Patents Worldwide Mixed-signal application-specific solutions
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Clustering Fabric Needs
Lowest Deterministic System Latency Scalability Peer to Peer / Any Topology Embedded Endpoints Energy Efficiency Cost per performance HW Reliability and Determinism Low Latency Hardware Terminated Guaranteed Delivery Scalability Ethernet PCIe PCIe Ethernet in software only RapidIO Interconnect combines the best attributes of PCIe® and Ethernet in a multi-processor fabric
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RapidIO Heterogeneous Computing clusters
Other nodes Heterogeneous compute workloads ARM, x86, OpenPower, No protocol termination CPU cycles 100 ns latency Distributed Switching Energy efficiency 20 to 50 Gbps embedded interconnect Mission critical reliability Build HPC systems tuned to workload Rack Scale Interconnect Fabric Cable / connector Local Inter- Connect Fabric FPGA/GPU CPU Storage Backplane Backplane Interconnect Fabric Other nodes Flexible Solutions Appliance Rack Scale
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10/20/40/50 Gbps per port – 6.25/10/12.5 Gps lane
Over 15 million RapidIO switches shipped > 2xEthernet (10GbE) Over 110 million Gbps ports shipped 100% 4G interconnect market share 60% 3G, 100% China 3G market share 10/20/40/50 Gbps per port – 6.25/10/12.5 Gps lane 100+ Gbps interconnect in definition Embedded RapidIO NIC on processors, DSPs, FPGA and ASICs. Hardware termination at PHY layer: 3 layer protocol Lowest Latency Interconnect ~ 100 ns Inherently scales to large system with 1000’s of nodes
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Supported by Large Eco-system
© 2015 RapidIO.org
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Open Compute Project HPC and Low Latency Interconnect
Supports Opencompute.org HPC Initiative
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HPC/Supercomputing Interconnect ‘Check In’
Requirements RapidIO Infiniband Ethernet PCIe The Meaning of Low Latency Switch silicon: ~100 nsec Memory to memory : < 1 usec Scalability Ecosystem supports any topology, 1000’s of nodes Integrated HW Termination Available integrated into SoCs AND Implement guaranteed, in order delivery without software Power Efficient 3 layers terminated in hardware, Integrated into SoC’s Fault Tolerant Ecosystem supports hot swap Ecosystem supports fault tolerance Deterministic Guaranteed, in order delivery Deterministic flow control Top Line Bandwidth Ecosystem supports > 8 Gbps/lane
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RapidIO Heterogeneous switch + server
External Panel With S-RIO and 10GigE 4x 20 Gbps RapidIO external ports 4x 10 GigE external Ports 4 processing mezzanine cards In chassis 320 Gbps of switching with 3 ports to each processing mezzanine Compute Nodes can use PCIe to S-RIO NIC Compute Node with ARM/PPC/DSP/FPGA are native RapidIO connected with small switching option on card Co located Storage over SATA 10 GbE added for ease of migration 19 Inch RapidIO Switch PCIe – S-RIO GPU DSP/ FPGA ARM CPU x86 CPU
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Quad Socket x86 HPC/Analytics Appliance
Ordering Now 4x 20 Gbps RapidIO external ports 4x 10 GigE external Ports 4 x Broadwell Sockets In chassis 320 Gbps of switching with 3 ports to each processing mezzanine Compute Nodes can use PCIe to S-RIO NIC Co located Storage over SATA 10 GbE added for ease of migration
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Acceleration with Mobile GPU Compute Node
Scalable Architecture GPU + Interconnect for Exascale 4 x Tegra K1 GPU RapidIO network 140 Gbps embedded RapidIO switching 4x PCIe2 to RapidIO NIC silicon 384 Gigaflops per GPU >1.5 Tflops per node 6 Teraflops per 1U 0.25 Petaflops per rack GPU compute acceleration
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Proposed: OCP Telco Low Latency Switch for Edge Computing Scale Out
Roadmap to 4.8 Tbps 2U 100 ns Switch With 50 Gbps ports 96 x 50 Gbps ports Sub 400W switching power Supports redundant ports to 42U rack and intra rack scale out 0.75 Tbps 1 U 19 Inch 100 ns Switch With 20 Gbps ports 38 x 20 Gbps ports Sub 200W switching power Support 42U Rack level scale out 5G|Mobile Edge Computing |HPC| Video Analytics | Low Latency Financial Trading
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OCP HPC Platform Use Case with RapidIO Fabric
RapidIO Low latency interconnect fabric for real time data center analytics at CERN Openlab Desire to leverage multi core heterogeneous computing x86, ARM, GPU, FPGA, DSP Collapse workloads and detect events with more certainty in real time: ex: particle collisions, fraud detection Use Industry standard Hardware from OCP Market emerges for real time compute analytics in data center
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Use of OCP HPC Designed Platforms
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Networking+Acceleration
Accelerator Card System topology: Server+ToR+ Networking+Acceleration RapidIO Top of Rack Switching 20 Gbps RapidIO PCIe Gen3 16 lanes PCIe Connector IDT RXS 1632 Switch IDT XO IDT UFT FPGA 1588 1588 s/w NIC RTL IDT S-RIO 50 Gbps RTL Hard Core PCIe MIP DDR4 IDT Tsi721 PCIe2 to S-RIO 50 Gbps 6x 50 Gbps Standard Server Socket X86/ARM OpenPower 19 Inch 1U or 2U rack mounted server IDT-FPGA Ref Design and System: Connects CPU to 50 Gbps RapidIO network
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Wrap Up Low latency 100ns switching Heterogeneous computing
Other nodes Rack Scale Interconnect Fabric Low latency 100ns switching Heterogeneous computing OCP HPC ready Emerging analytics workloads energy efficient high bandwidth interconnect Ideal for HPC and HPC like apps such as financial computing Cable / connector Local Inter- Connect Fabric FPGA/GPU CPU Storage Backplane Backplane Interconnect Fabric 20 Gbps per port now 50 Gbps released 100 Gbps in definition Other nodes
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