1. Using CAD Tools to implement Digital Circuits
10/6/08
ECE Lecture 7

2. Overview Schematic Capture
HDL implementation/specification/code for the sequential machine
10/6/08
ECE Lecture 7

3. Starting Point Problem Statement/Specification
Needs to be correct
Needs to be complete
Translation from problem statement to state/transition table or state diagram
One of the most important steps today
10/6/08
ECE Lecture 7

4. Schematic Capture Must work through to excitation and output equations
Having these – can create circuit schematic that can be captured in Xilinx ISE or Altera Quartis
10/6/08
ECE Lecture 7

5. Example from before Next state and output equations
D1 = Q2 X’ Y + Q1’ X Y + Q1 X’ Y’ + Q2 X Y’
Z = Q1’ Q2’
D2 = Q1’ X’ Y + Q1’ X Y’ + Q2 X’ Y’ + Q2 X Y
10/6/08
ECE Lecture 7

6. Implementation
Needs to be completed
10/6/08
ECE Lecture 7

7. HDL Capture For VHDL, need only use a subset of the language
Rigid style allows for a “shell” approach for writing state machines that synthesize well
Have 2 parts
The Entity – the interface to the state machine
The Architecture – the interior or the function
10/6/08
ECE Lecture 7

8. The Entity Can be done in the following style
ENTITY descriptor IS
port ( port list );
END descriptor;
Port list is a specification of the inputs and output, their direction and type.
10/6/08
ECE Lecture 7

9. Simple Port List Mode–the direction of transfer – IN or OUT
Signal Name – your choice
Names start with a letter and are alphanumeric after that
Cannot use reserved words of language
Signal Type – for simplicity will just use type BIT which has values of ‘0’ and ‘1’
10/6/08
ECE Lecture 7

10. Example And example for a state machine ENTITY example_1 IS
PORT (X,Y : IN BIT;
R : OUT BIT;
CLK : IN BIT);
END example_1;
10/6/08
ECE Lecture 7

11. The Architecture
The architecture design unit is where the function of the state machine is specified.
Is easiest to think of state machines as composed of three parts
10/6/08
ECE Lecture 7

12. For VHDL Will keep each of these units distinct
The next state logic
The F/F
The output logic
Will use a process language structure process for each
Within each the VHDL used is much like any other language
10/6/08
ECE Lecture 7

13. F/F Specification --The structure to specify the F/F PROCESS BEGIN
WAIT UNTIL clk=‘1’ and clk’event;
state <= next_state;
END PROCESS;
10/6/08
ECE Lecture 7

14. The next state process Code for specification of the next state
10/6/08
ECE Lecture 7

15. The next state process
Note that you never get to actual logic equations.
You simply use a state table where the states are A,B,C,….
Similarly, you do not get to state encoding. You use pneumonic representation for the states. Here they are idle, l1, l2, l3, r1, r2, r3, lr3
10/6/08
ECE Lecture 7

16. The output process
A third process and similar in structure to the next state process.
10/6/08
ECE Lecture 7

17. Where to put the processes?
The processes are held in the ARCHECTURE design unit.
ARCHECTURE one OF example_1 IS
-- Local Declarations
TYPE state_type IS (idle,l1,l2,l3,r1,r2,r3,lr3);
SIGNAL state, next_state : state_type;
BEGIN
-- and now come the three processes in any order
END one;
10/6/08
ECE Lecture 7

18. Next
More on Language Elements for specifying next state and output logic.
An example of HDL state machine implementation
10/6/08
ECE Lecture 7