Microcomputer Systems 1

Microcomputer Systems 1
Digital Systems: Hardware Organization and Design 9/22/2018 Microcomputer Systems 1 ADSP-BF533 Ez-Kit Lite Audio Interface Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design
9/22/2018 Lab #5 Audio Interface 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

ADSP-BF533 Ez-Kit Lite Audio Interface
Digital Systems: Hardware Organization and Design 9/22/2018 ADSP-BF533 Ez-Kit Lite Audio Interface SPI SPORT0 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

BF533 EZ-Kit Lite – Audio Interface
Digital Systems: Hardware Organization and Design 9/22/2018 BF533 EZ-Kit Lite – Audio Interface EZ-Kit Lite contains AD1836 Audio Codec The AD1836 audio codec provides three channels of stereo audio output and two channels of multi-channel/stereo 96 kHz input. The SPORT0 interface of the processor links with the stereo audio data input and output pins of the AD1836 codec. The processor is capable of transferring data to the audio codec in time-division multiplexed (TDM) or two-wire interface (TWI) mode. The TDM mode can operate at a maximum of 48 kHz sample rate but allows simultaneous use of all input and output channels. The TWI mode allows the codec to operate at a 96 kHz sample rate but limits the output channels to two. When using TWI mode, the TSCLK0 and RSCLK0 pins, as well as the TFS0 and RFS0 pins of the processor, must be tied together external to the processor. This is accomplished with the SW9 DIP switch (see “Push Button Enable Switch (SW9)” on page 2-12 for more information). 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Blackfin Audio Interface Usage
Digital Systems: Hardware Organization and Design 9/22/2018 Blackfin Audio Interface Usage Two-Wire Interface (TWI) and Serial Peripheral Interface (SPI) Forward channel used to configure and control audio converters Reverse channel relays feedback info from converters SPORT’s Used as data channel for audio data SPORT TX connects to audio DAC SPORT RX connects to audio ADC Full-duplex SPORT RX/TX connects to audio codec In some codecs (e.g., AC97), SPORT also can serve as the codec control channel 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 BF533 Interface with AD1871 Data Transfer & Synch Configuration & Control 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SW9 Switch Configuration
Digital Systems: Hardware Organization and Design 9/22/2018 SW9 Switch Configuration Make sure that SW9 switches 5 and 6 are ON & SW12 is ON. See explanation bellow: 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Switch Default Configuration
Digital Systems: Hardware Organization and Design 9/22/2018 Switch Default Configuration 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Push-buttons and LED’s
Digital Systems: Hardware Organization and Design 9/22/2018 Push-buttons and LED’s 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Push Button Enable Switch (SW9 & SW12)
Digital Systems: Hardware Organization and Design 9/22/2018 Push Button Enable Switch (SW9 & SW12) SW9 Positions 1 through 4: Disconnects the drivers associated with the push buttons from the PF pins of the processor. Positions 5 and 6: Used to connect the transmit and receive frame syncs and clocks of SPORT0. This is important when the AD1836 audio/video decoder and the processor are communicating in I2S mode. SW12 When is set to OFF, SW12 disconnects SPORT0 from the audio codec. The default is the ON position. Table 2-6 in the next slide shows which PF is driven when the switch is in the default (ON) position. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Push Button Enable Switch (SW9)
Digital Systems: Hardware Organization and Design 9/22/2018 Push Button Enable Switch (SW9) Table 2-6 shows which PF is driven when the switch is in the default (ON) position 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORT0 interface to AD1836 audio codec
Digital Systems: Hardware Organization and Design 9/22/2018 SPORT0 interface to AD1836 audio codec The SPORT0 connects to the AD1836 audio codec and the expansion interface. The AD1836 codec uses both the primary and secondary data transmit and receive pins to input and output data from the audio inputs and outputs. The SPORT1 connects to the SPORT connector (P3) and the expansion interface. The pinout of the SPORT connector and the expansion interface connectors can be found in “ADSP-BF533 EZ-KIT Lite Schematic” on page B-1. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

The pin layout of the SPORT connector & expansion interface connectors
Digital Systems: Hardware Organization and Design 9/22/2018 The pin layout of the SPORT connector & expansion interface connectors SW12 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Audio Interface Configuration
Digital Systems: Hardware Organization and Design 9/22/2018 Audio Interface Configuration The AD1836 audio codec’s internal configuration registers are configured using the Serial Port Interface - SPI port of the processor (see Slide #6). The processor’s PF4 - programmable flag pin is used as the select for this device. For information on how to configure the multi-channel codec, go to 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Audio Interface and Programmable Flags
Digital Systems: Hardware Organization and Design 9/22/2018 Audio Interface and Programmable Flags The processor has 15 programmable flag pins (PF’s). The pins are multifunctional and depend on the processor setup. Table 2-1 in the ADSP-BF533 EZ-KIT Lite Evaluation System Manual provides the summary of the programmable flag pins used on the EZ-Kit Lite. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Programmable Flag Connections
Digital Systems: Hardware Organization and Design 9/22/2018 Programmable Flag Connections 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Audio Interface Configuration (cont.)
Digital Systems: Hardware Organization and Design 9/22/2018 Audio Interface Configuration (cont.) The general-purpose IO pin PA0 of flash A is a source for the AD1836 codec reset. See “Flash General-Purpose IO” on page 1-12 for more information about the pin of ADSP-BF533 EZ-KIT Lite Evaluation System Manual. Also information given in the next slide. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 AD1836 codec reset via PA0 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Flash General-Purpose IO
Digital Systems: Hardware Organization and Design 9/22/2018 Flash General-Purpose IO General-purpose IO signals are controlled by means of setting appropriate registers of the flash A or flash B. These registers are mapped into the processor’s address space, as shown in the Table below (ADSP-BF533 EZ-KIT Lite Evaluation System Manual – Flash Memory) 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Flash General-Purpose IO
Digital Systems: Hardware Organization and Design 9/22/2018 Flash General-Purpose IO Flash device IO pins are arranged as 8-bit ports labeled A through G. There is a set of 8-bit registers associated with each port. These registers are Direction, Data In, and Data Out. Note that the Direction and Data Out registers are cleared to all zeros at power-up or hardware reset. The Direction register controls IO pins direction. This is a 8-bit read-write register. When a bit is 0, a corresponding pin functions as an input. When the bit is 1, a corresponding pin is an output. The Data In register allows reading the status of port’s pins. This is a 8-bit read-only register. The Data Out register allows clearing an output pin to 0 or setting it to 1. This is a 8-bit read-write register. The ADSP-BF533 EZ-KIT Lite board employs only flash A and flash B ports A and B. Table 1-5 and Table 1-6 provide configuration register addresses for flash A and flash B, respectively (only ports A and B are listed in the next slide). The following bits connect to the expansion board connector. Flash A: port A bits 7 and 6, as well as port B bits 7 and 6 Flash B: port A bits 7–0 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Flash A & B Configuration Registers for Ports A and B.
Digital Systems: Hardware Organization and Design 9/22/2018 Flash A & B Configuration Registers for Ports A and B. Table 1-5. Flash A Configuration Registers for Ports A and B Table 1-6. Flash B Configuration Registers for Ports A and B Register Name Port A Address Port B Address Data In (read-only) 0x 0x Data Out (read-write) 0x 0x Direction (read-write) 0x 0x Register Name Port A Address Port B Address Data In (read-only) 0x202E 0000 0x202E 0001 Data Out (read-write) 0x202E 0004 0x202E 0005 Direction (read-write) 0x202E 0006 0x202E 0007 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

IO Assignments for Port A and B
Digital Systems: Hardware Organization and Design 9/22/2018 IO Assignments for Port A and B Table 1-7 Flash A Port A Controls. Bit Number User IO Bit Value 7 Not defined Any 6 5 PPI clock select bit 1 00=local OSC (27MHz) 4 PPI clock select bit 0 01=video decoder pixel clock 1x=expansion board PPI clock 3 Video decoder reset 0=reset ON; 1=reset OFF 2 Video encoder reset 1 Reserved Codec reset 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 Talk-Through Analysis of Lab Exercise Architecture of a Respresentative 32 Bit Processor

9/22/2018 main.c // // // // // Name: Talkthrough for the ADSP-BF533 EZ-KIT Lite // // (C) Copyright Analog Devices, Inc. All rights reserved // // Project Name: BF533 C Talkthrough TDM // // Date Modified: 04/03/03 HD Rev // // Software: VisualDSP // // Hardware: ADSP-BF533 EZ-KIT Board // // Connections: Connect an input source (such as a radio) to the Audio // // input jack and an output source (such as headphones) to // // the Audio output jack // // // // Purpose: This program sets up the SPI port on the ADSP-BF533 to // // configure the AD1836 codec. The SPI port is disabled // // after initialization. The data to/from the codec are // // transfered over SPORT0 in TDM mode // #include "Talkthrough.h" #include "sysreg.h" #include "ccblkfn.h" #include <btc.h> 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 Talkthrough.h #ifndef __Talkthrough_DEFINED #define __Talkthrough_DEFINED // // // Header files // #include <sys\exception.h> #include <cdefBF533.h> #include <ccblkfn.h> #include <sysreg.h> // Symbolic constants // // addresses for Port B in Flash A #define pFlashA_PortA_Dir (volatile unsigned char *)0x #define pFlashA_PortA_Data (volatile unsigned char *)0x // names for codec registers, used for iCodec1836TxRegs[] #define DAC_CONTROL_1 0x0000 #define DAC_CONTROL_2 0x1000 #define DAC_VOLUME_0 0x2000 #define DAC_VOLUME_1 0x3000 #define DAC_VOLUME_2 0x4000 #define DAC_VOLUME_3 0x5000 #define DAC_VOLUME_4 0x6000 #define DAC_VOLUME_5 0x7000 #define ADC_0_PEAK_LEVEL x8000 #define ADC_1_PEAK_LEVEL x9000 #define ADC_2_PEAK_LEVEL xA000 #define ADC_3_PEAK_LEVEL xB000 #define ADC_CONTROL_1 0xC000 #define ADC_CONTROL_2 0xD000 #define ADC_CONTROL_3 0xE000 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Flash A & B Configuration Registers for Ports A and B.
Digital Systems: Hardware Organization and Design 9/22/2018 Flash A & B Configuration Registers for Ports A and B. Table 1-5. Flash A Configuration Registers for Ports A and B Table 1-6. Flash B Configuration Registers for Ports A and B Register Name Port A Address Port B Address Data In (read-only) 0x 0x Data Out (read-write) 0x 0x Direction (read-write) 0x 0x Register Name Port A Address Port B Address Data In (read-only) 0x202E 0000 0x202E 0001 Data Out (read-write) 0x202E 0004 0x202E 0005 Direction (read-write) 0x202E 0006 0x202E 0007 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 DAC Control Register 1 & 2 From: AD1836A Multi-channel Codec Manual #define DAC_CONTROL_1 0x0000 #define DAC_CONTROL_2 0x1000 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

DAC Volume Control Registers
Digital Systems: Hardware Organization and Design 9/22/2018 DAC Volume Control Registers #define DAC_VOLUME_0 0x2000 #define DAC_VOLUME_1 0x3000 #define DAC_VOLUME_2 0x4000 #define DAC_VOLUME_3 0x5000 #define DAC_VOLUME_4 0x6000 #define DAC_VOLUME_5 0x7000 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

ADC Peak Level Registers
Digital Systems: Hardware Organization and Design 9/22/2018 ADC Peak Level Registers #define ADC_0_PEAK_LEVEL x8000 #define ADC_1_PEAK_LEVEL x9000 #define ADC_2_PEAK_LEVEL xA000 #define ADC_3_PEAK_LEVEL xB000 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 ADC Control Register 1 #define ADC_CONTROL_1 0xC000 #define ADC_CONTROL_2 0xD000 #define ADC_CONTROL_3 0xE000 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 Talkthrough.h (cont. 1) // names for slots in ad1836 audio frame #define INTERNAL_ADC_L0 0 #define INTERNAL_ADC_L1 1 #define INTERNAL_ADC_R0 4 #define INTERNAL_ADC_R1 5 #define INTERNAL_DAC_L0 0 #define INTERNAL_DAC_L1 1 #define INTERNAL_DAC_L2 2 #define INTERNAL_DAC_R0 4 #define INTERNAL_DAC_R1 5 #define INTERNAL_DAC_R2 6 // size of array iCodec1836TxRegs and iCodec1836RxRegs #define CODEC_1836_REGS_LENGTH 11 // SPI transfer mode #define TIMOD_DMA_TX 0x0003 // SPORT0 word length #define SLEN_32 0x001f // DMA flow mode #define FLOW_1 0x1000 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 Talkthrough.h (cont. 2) // // // Global variables // extern int iChannel0LeftIn; extern int iChannel0RightIn; extern int iChannel0LeftOut; extern int iChannel0RightOut; extern int iChannel1LeftIn; extern int iChannel1RightIn; extern int iChannel1LeftOut; extern int iChannel1RightOut; extern volatile short sCodec1836TxRegs[]; extern volatile int iRxBuffer1[]; extern volatile int iTxBuffer1[]; // Prototypes // // in file Initialisation.c void Init_EBIU(void); void Init_Flash(void); void Init1836(void); void Init_Sport0(void); void Init_DMA(void); void Init_Sport_Interrupts(void); void Enable_DMA_Sport0(void); // in file Process_data.c void Process_Data(void); // in file ISRs.c EX_INTERRUPT_HANDLER(Sport0_RX_ISR); #endif //__Talkthrough_DEFINED 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 main.c #include "Talkthrough.h" #include "sysreg.h" #include "ccblkfn.h" #include <btc.h> // // // Variables // // // // Description: The variables iChannelxLeftIn and iChannelxRightIn contain // // the data coming from the codec AD The (processed) // // playback data are written into the variables // // iChannelxLeftOut and iChannelxRightOut respectively, which // // are then sent back to the codec in the SPORT0 ISR // // The values in the array iCodec1836TxRegs can be modified to // // set up the codec in different configurations according to // // the AD1885 data sheet // // left input data from ad1836 int iChannel0LeftIn, iChannel1LeftIn; // right input data from ad1836 int iChannel0RightIn, iChannel1RightIn; // left ouput data for ad1836 int iChannel0LeftOut, iChannel1LeftOut; // right ouput data for ad1836 int iChannel0RightOut, iChannel1RightOut; 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 main.c (cont 1) // array for registers to configure the ad1836 names are defined in "Talkthrough.h" volatile short sCodec1836TxRegs[CODEC_1836_REGS_LENGTH] = { DAC_CONTROL_1 | 0x000, DAC_CONTROL_2 | 0x000, DAC_VOLUME_0 | 0x3ff, DAC_VOLUME_1 | 0x3ff, DAC_VOLUME_2 | 0x3ff, DAC_VOLUME_3 | 0x3ff, DAC_VOLUME_4 | 0x3ff, DAC_VOLUME_5 | 0x3ff, ADC_CONTROL_1 | 0x000, ADC_CONTROL_2 | 0x180, ADC_CONTROL_3 | 0x000 }; #define DAC_VOLUME_0 0x2000 | 0x3ff = 0x23ff #define DAC_VOLUME_1 0x3000 | 0x3ff = 0x33ff #define DAC_VOLUME_2 0x4000 | 0x3ff = 0x43ff #define DAC_VOLUME_3 0x5000 | 0x3ff = 0x53ff #define DAC_VOLUME_4 0x6000 | 0x3ff = 0x63ff #define DAC_VOLUME_5 0x7000 | 0x3ff = 0x73ff #define DAC_CONTROL_1 0x0000 | 0x000 = 0x0000 #define DAC_CONTROL_2 0x1000 | 0x000 = 0x1000 #define ADC_CONTROL_1 0xC000 | 0x000 = 0xC000 #define ADC_CONTROL_2 0xD000 | 0x180 = 0xD180 #define ADC_CONTROL_3 0xE000 | 0x000 = 0xE000 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 ADC Master Mode 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 ADC Slave Mode 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 main.c (cont 2) // SPORT0 DMA transmit buffer volatile int iTxBuffer1[8]; // SPORT0 DMA receive buffer volatile int iRxBuffer1[8]; //////////////////// // BTC Definitions #define MAXBTCBUF int BTCLeft[MAXBTCBUF]; int BTCRight[MAXBTCBUF]; int BTCLeftVolume = 0; int BTCRightVolume = 0; BTC_MAP_BEGIN // Channel Name, Starting Address, Length (bytes) BTC_MAP_ENTRY("Audio Left Channel", (long)&BTCLeft, sizeof(BTCLeft)) BTC_MAP_ENTRY("Audio Right Channel", (long)&BTCRight, sizeof(BTCRight)) BTC_MAP_ENTRY("Audio Left Volume", (long)&BTCLeftVolume, sizeof(BTCLeftVolume)) BTC_MAP_ENTRY("Audio Right Volume", (long)&BTCRightVolume, sizeof(BTCRightVolume)) BTC_MAP_END 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 main.c (cont. 3) // // // Function: main // // // // Description: After calling a few initalization routines, main() just // // waits in a loop forever. The code to process the incoming // // data can be placed in the function Process_Data() in the // // file "Process_Data.c" // void main(void) { sysreg_write(reg_SYSCFG, 0x32); //Initialize System Configuration Register Init_EBIU(); Init_Flash(); Init1836(); Init_Sport0(); Init_DMA(); Init_Sport_Interrupts(); Enable_DMA_Sport0(); btc_init(); while(1) { btc_poll(); } 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Background Telemetry Channels (BTCs)
Digital Systems: Hardware Organization and Design 9/22/2018 Background Telemetry Channels (BTCs) Background telemetry channels (BTCs) enable VisualDSP++ and a processor to exchange data via the JTAG interface while the processor is executing. Before BTC, all communication between VisualDSP++ and a processor took place while the processor was in a halted state. Note: Background telemetry channels are supported only in SHARC and Blackfin emulator sessions. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

BTC Definitions in the Program
Digital Systems: Hardware Organization and Design 9/22/2018 BTC Definitions in the Program Background telemetry channels are defined on a per program (.DXE) basis. The channels are defined when a specific program is loaded onto a processor. BTC channels are defined in a program by using simple macros. The following example code shows channel definitions. #include "btc.h“ BTC_MAP_BEGIN // Channel Name, Starting Address, Length (bytes) BTC_MAP_ENTRY("Audio Left Channel", (long)&BTCLeft, sizeof(BTCLeft)) BTC_MAP_ENTRY("Audio Right Channel", (long)&BTCRight, sizeof(BTCRight)) BTC_MAP_ENTRY("Audio Left Volume", (long)&BTCLeftVolume, sizeof(BTCLeftVolume)) BTC_MAP_ENTRY("Audio Right Volume", (long)&BTCRightVolume, sizeof(BTCRightVolume)) BTC_MAP_END The first step in defining channels in a program is to include the BTC macros by using the #include btc.h statement. Then each channel is defined with the macros. The definitions begin with BTC_MAP_BEGIN, which marks the beginning of the BTC map. Next, each individual channel is defined with the BTC_MAP_ENTRY macro, which takes the parameters described in Table 2-17 in VisualDSP User’s Guide. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 BTC_MAP_ENTRY Macro 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 Initialize.c EBIU setup Timer setup FIO setup Flash setup Interrupt configuration Endless loop waiting for Timer interrupt or Flag interrupt Architecture of a Respresentative 32 Bit Processor

External Bus Interface Unit (EBIU) Setup
Digital Systems: Hardware Organization and Design 9/22/2018 External Bus Interface Unit (EBIU) Setup #include "Talkthrough.h" // // // Function: Init_EBIU // // // // Description: This function initializes and enables asynchronous memory // // banks in External Bus Interface Unit so that Flash A can be // // accessed // void Init_EBIU(void) { *pEBIU_AMBCTL0 = 0x7bb07bb0; *pEBIU_AMBCTL1 = 0x7bb07bb0; *pEBIU_AMGCTL = 0x000f; } 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

External Bus Interface Unit
Digital Systems: Hardware Organization and Design 9/22/2018 External Bus Interface Unit The EBIU services requests for external memory from the Core or from a DMA channel. The priority of the requests is determined by the External Bus Controller. The address of the request determines whether the request is serviced by the EBIU SDRAM Controller or the EBIU Asynchronous Memory Controller. The EBIU is clocked by the system clock (SCLK). All synchronous memories interfaced to the processor operate at the SCLK frequency. The ratio between core frequency and SCLK frequency is programmable using a phase-locked loop (PLL) system memory-mapped register (MMR). 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

EBIU Programming Model
Digital Systems: Hardware Organization and Design 9/22/2018 EBIU Programming Model This programming model is based on system memory-mapped registers used to program the EBIU. There are six control registers and one status register in the EBIU. They are: Asynchronous Memory Global Control register (EBIU_AMGCTL) Asynchronous Memory Bank Control 0 register (EBIU_AMBCTL0) Asynchronous Memory Bank Control 1 register (EBIU_AMBCTL1) SDRAM Memory Global Control register (EBIU_SDGCTL) SDRAM Memory Bank Control register (EBIU_SDBCTL) SDRAM Refresh Rate Control register (EBIU_SDRRC) SDRAM Control Status register (EBIU_SDSTAT) 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

The Asynchronous Memory Interface
Digital Systems: Hardware Organization and Design 9/22/2018 The Asynchronous Memory Interface The asynchronous memory interface allows interfaceing to a variety of memory and peripheral types. These include SRAM, ROM, EPROM, flash memory, and FPGA/ASIC designs. Four asynchronous memory regions are supported. Each has a unique memory select associated with it, shown in Table 17-3. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Asynchronous Memory Bank Address Range
Digital Systems: Hardware Organization and Design 9/22/2018 Asynchronous Memory Bank Address Range 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 EBIU_AMGCTL Register The Asynchronous Memory Global Control register (EBIU_AMGCTL) configures global aspects of the controller. The EBIU_AMGCTL register should be the last control register written to when configuring the processor to access external memory-mapped asynchronous devices. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 Initialization.c // // // Function: Init_EBIU // // // // Parameters: None // // Return: None // // Description: This function initializes and enables the asynchronous // // memory banks for the External Bus Interface Unit (EBIU), so // // that access to Flash A is possible // void Init_EBIU(void) { *pEBIU_AMBCTL0 = 0x7bb07bb0; *pEBIU_AMBCTL1 = 0x7bb07bb0; *pEBIU_AMGCTL = 0x000f; } Asynchronous Memory Global Control Register 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Asynchronous Memory Global Control Register EBIU_AMGCTL
Digital Systems: Hardware Organization and Design 9/22/2018 Asynchronous Memory Global Control Register EBIU_AMGCTL 0x000f = 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 Initialization.c // // // Function: Init_EBIU // // // // Parameters: None // // Return: None // // Description: This function initializes and enables the asynchronous // // memory banks for the External Bus Interface Unit (EBIU), so // // that access to Flash A is possible // void Init_EBIU(void) { *pEBIU_AMBCTL0 = 0x7bb07bb0; *pEBIU_AMBCTL1 = 0x7bb07bb0; *pEBIU_AMGCTL = 0x000f; } Asynchronous Memory Control Register 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

EBIU_AMBCTL0 and EBIU_AMBCTL1 Registers
Digital Systems: Hardware Organization and Design 9/22/2018 EBIU_AMBCTL0 and EBIU_AMBCTL1 Registers The EBIU asynchronous memory controller has two Asynchronous Memory Bank Control registers: EBIU_AMBCTL0 and EBIU_AMBCTL1. They contain bits for counters for: setup, strobe, and hold time; bits to determine memory type and size; and bits to configure use of ARDY. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Asynchronous Memory Bank Control 0 Register
Digital Systems: Hardware Organization and Design 9/22/2018 Asynchronous Memory Bank Control 0 Register 0x7bb07bb0 = 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 External Memory Map The three SDRAM control registers must be initialized in order to use the MT48LC32M16 – 64 MB (32M x 16 bits) SDRAM memory of EZ-Kit Lite: EBIU_SDGCTL: SDRAM Memory Global Control register EBIU_SDBCTL: SDRAM Memory Bank Control register EBIU_SDRRC: SDRAM Refresh Rate Control register The External Memory Map supported by BF533 is provided in the Figure 17-1. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 EBIU_SDGCTL Register The SDRAM Memory Global Control register (EBIU_SDGCTL) includes all programmable parameters associated with the SDRAM access timing and configuration. Figure shows the EBIU_SDGCTL register bit definitions. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SDRAM Memory Global Control register: EBIU_SDGCTL
Digital Systems: Hardware Organization and Design 9/22/2018 SDRAM Memory Global Control register: EBIU_SDGCTL 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 Initialize.c EBIU setup Flash setup FIO setup Interrupt configuration Endless loop waiting for Timer interrupt or Flag interrupt Architecture of a Respresentative 32 Bit Processor

9/22/2018 Initialize.c // // // Function: Init_Flash // // // // Description: This function initializes pin direction of Port A in Flash A // // to output. The AD1836_RESET on the ADSP-BF533 EZ-KIT board // // is connected to Port A // void Init_Flash(void) { *pFlashA_PortA_Dir = 0x1; } 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 Initialize.c // // // Function: Init_Flash // // // // Description: This function initializes pin direction of Port A in Flash A // // to output. The AD1836_RESET on the ADSP-BF533 EZ-KIT board // // is connected to Port A // void Init_Flash(void) { *pFlashA_PortA_Dir = 0x1; } Direction Configuration 0x1 = 0001 The Direction register controls IO pins direction. This is a 8-bit read-write register. When a bit is 0, a corresponding pin functions as an input. When the bit is 1, a corresponding pin is an output. See Slide #13 for details or EZ-Kit Lite HRM. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 Initialize.c EBIU setup Flash setup SPI setup for ADC1836 FIO setup Interrupt configuration Endless loop waiting for Timer interrupt or Flag interrupt Architecture of a Respresentative 32 Bit Processor

9/22/2018 Initialize.c // // // Function: Init1836() // // // // Description: This function sets up the SPI port to configure the AD1836. // // The content of the array sCodec1836TxRegs is sent to the // // codec // void Init1836(void) { int i; int j; static unsigned char ucActive_LED = 0x01; // write to Port A to reset AD1836 *pFlashA_PortA_Data = 0x00; // write to Port A to enable AD1836 *pFlashA_PortA_Data = ucActive_LED; // wait to recover from reset for (i=0; i<0xf000; i++); // Enable PF4 *pSPI_FLG = FLS4; // Set baud rate SCK = HCLK/(2*SPIBAUD) SCK = 2MHz *pSPI_BAUD = 16; // configure spi port // SPI DMA write, 16-bit data, MSB first, SPI Master *pSPI_CTL = TIMOD_DMA_TX | SIZE | MSTR; Reset AD1836 ADC & DAC Codec. Activate AD1836 Via PF4 pin Setting the Baud Rate of the Codec Setting the DMA transfer 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Serial Peripheral Interface (SPI)
Digital Systems: Hardware Organization and Design 9/22/2018 Serial Peripheral Interface (SPI) The processor has a Serial Peripheral Interface (SPI) port that provides an I/O interface to a wide variety of SPI compatible peripheral devices. SPI is a four-wire interface consisting of two data pins (IN & OUT), a device select pin (SPISS), and a clock (CLK) pin. SPI is a full-duplex synchronous serial interface, supporting master modes, slave modes, and multimaster environments. The SPI compatible peripheral implementation also supports programmable baud rate and clock phase/polarities. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/22/2018 Serial Peripheral Interface (SPI) Typical SPI compatible peripheral devices that can be used to interface to the SPI compatible interface include: Other CPUs or microcontrollers Codecs A/D converters D/A converters Sample rate converters SP/DIF or AES/EBU digital audio transmitters and receivers LCD displays Shift registers FPGAs with SPI emulation 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/22/2018 Serial Peripheral Interface (SPI) The SPI is an industry-standard synchronous serial link that supports communication with multiple SPI compatible devices. The SPI peripheral is a synchronous, four-wire interface consisting of two data pins: Master Out Slave In (MOSI) and Master In Slave Out (MISO) one device select pin Serial Peripheral Interface Slave Select (SPISS) Input Signal, and a gated clock pin Serial Peripheral Interface Clock (SCK) Signal. With the two data pins, it allows for full-duplex operation to other SPI compatible devices. The SPI also includes programmable baud rates, clock phase, and clock polarity. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/22/2018 Serial Peripheral Interface (SPI) The SPI can operate in a multimaster environment by interfacing with several other devices, acting as either a master device or a slave device. Figure 10-1 provides a block diagram of the SPI. The interface is essentially a shift register that serially transmits and receives data bits, one bit at a time at the SCK rate, to and from other SPI devices. SPI data is transmitted and received at the same time through the use of a shift register. When an SPI transfer occurs, data is simultaneously transmitted (shifted serially out of the shift register) as new data is received (shifted serially into the other end of the same shift register). The SCK synchronizes the shifting and sampling of the data on the two serial data pins. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 SPI Block Diagram 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 SPI Interface Signals Architecture of a Respresentative 32 Bit Processor

Serial Peripheral Interface Clock Signal (SCK)
Digital Systems: Hardware Organization and Design 9/22/2018 Serial Peripheral Interface Clock Signal (SCK) The SCK signal is the SPI clock signal. This control signal is driven by the master and controls the rate at which data is transferred. The master may transmit data at a variety of baud rates. The SCK signal cycles once for each bit transmitted. It is an output signal if the device is configured as a master, and an input signal if the device is configured as a slave. The SCK is a gated clock that is active during data transfers only for the length of the transferred word. The number of active clock edges is equal to the number of bits driven on the data lines. Slave devices ignore the serial clock if the Serial Peripheral Slave Select Input (SPISS’) is driven inactive (high). The SCK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on active edges of the clock and sampled on inactive edges of the clock. Clock polarity and clock phase relative to data are programmable in the SPI Control register (SPI_CTL) and define the transfer format. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Serial Peripheral Interface Slave Select Input Signal
Digital Systems: Hardware Organization and Design 9/22/2018 Serial Peripheral Interface Slave Select Input Signal The SPISS’ signal is the SPI Serial Peripheral Slave Select Input signal. This is an active-low signal used to enable a processor when it is configured as a slave device. This input-only pin behaves like a chip select and is provided by the master device for the slave devices. For a master device, it can act as an error signal input in case of the multimaster environment. In multimaster mode, if the SPISS input signal of a master is asserted (driven low), and the PSSE bit in the SPI_CTL register is enabled, an error has occurred. This means that another device is also trying to be the master device. Note: The SPISS signal is the same pin as the PF0 pin. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Master Out Slave In (MOSI) & Master In Slave Out (MISO)
Digital Systems: Hardware Organization and Design 9/22/2018 Master Out Slave In (MOSI) & Master In Slave Out (MISO) Master Out Slave In (MOSI) The MOSI pin is the Master Out Slave In pin, one of the bidirectional I/O data pins. If the processor is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the processor is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data. In an SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). Master In Slave Out (MISO) The MISO pin is the Master In Slave Out pin, one of the bidirectional I/O data pins. If the processor is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the processor is configured as a slave, the MISO pin becomes a data transmit (output) pin, 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

ADSP-BF533 as Slave SPI Device
Digital Systems: Hardware Organization and Design 9/22/2018 ADSP-BF533 as Slave SPI Device 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 Interrupt Output The SPI has two interrupt output signals: a data interrupt and an error interrupt 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPI Data Interrupt Output
Digital Systems: Hardware Organization and Design 9/22/2018 SPI Data Interrupt Output The behavior of the SPI data interrupt signal depends on the Transfer Initiation Mode bit field (TIMOD) in the SPI Control register (discussed next). In DMA mode (TIMOD = 1X), the data interrupt acts as a DMA request and is generated when the DMA FIFO is ready to be written to (TIMOD = 11) or read from (TIMOD = 10). In non-DMA mode (TIMOD = 0X), a data interrupt is generated when the SPI_TDBR is ready to written to (TIMOD = 01) or when the SPI_RDBR is ready to be read from (TIMOD = 00). 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPI Error Interrupt Output
Digital Systems: Hardware Organization and Design 9/22/2018 SPI Error Interrupt Output An SPI Error interrupt is generated in a master when a Mode Fault Error occurs, in both DMA and non-DMA modes. An error interrupt can also be generated in DMA mode when there is an underflow (TXE when TIMOD = 11) or an overflow (RBSY when TIMOD = 10) error condition. In non-DMA mode, the underflow and overflow conditions set the TXE and RBSY bits in the SPI_STAT register, respectively, but do not generate an error interrupt. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 SPI Registers The SPI peripheral includes a number of user-accessible registers. Some of these registers are also accessible through the DMA bus. Four registers contain control and status information: SPI_BAUD, SPI_CTL, SPI_FLG, and SPI_STAT. Two registers are used for buffering receive and transmit data: SPI_RDBR and SPI_TDBR For information about DMA-related registers, see Chapter 9 of ADSP-BF533 Blackfin Processor Hardware Reference, “Direct Memory Access.” also discussed next. The shift register, SFDR, is internal to the SPI module and is not directly accessible. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPI Registers: SPI_BAUD Register
Digital Systems: Hardware Organization and Design 9/22/2018 SPI Registers: SPI_BAUD Register The SPI Baud Rate register (SPI_BAUD) is used to set the bit transfer rate for a master device. When configured as a slave, the value written to this register is ignored. The serial clock frequency is determined by this formula: SCK Frequency = (Peripheral clock frequency SCLK)/(2 x SPI_BAUD) SCK – Clock Divide Factor SPI_BAUD = 16 & assuming SCLK = 100 MHz ⇒ SCK = 100 MHz/32 = 3125 Hz. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 SPI_BAUD Register 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Note on SPORT Clock division and frame sync
Digital Systems: Hardware Organization and Design 9/22/2018 Note on SPORT Clock division and frame sync The clock division parameters are located in the SPORTx_TCLKDIV and SPORTx_RCLKDIV registers. To specify a clock frequency for the SPORT, use the following equation: Where: f(sclk) is the frequency of the core (~52 Mhz default on the EZ-KIT LITE), SPORTx_yCLK (y is T - for transmit, R – for receive) frequency is the specified clock frequency of the SPORT, and SPORTx_yCLKDIV is the value needed to be input into the specified transmit/receive clock division register. Frame sync parameters are the number of serial clock cycles before a frame sync is generated. This value must not be less than the serial word length (SLEN), otherwise corrupt data will be received. # of serial clock cycles between frame syncs = SPORTx_yFSDIV + 1 For example, if one wanted a serial clock frequency of 375 kHz, and 32 bit words were used, then SPORTx_yCLKDIV = 52MHz/(2*375kHz) - 1 = = 69 = 0x0045 SPORTx_yFSDIV = = 31 = 0x001f 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 SPI_CTL Register The SPI Control register (SPI_CTL) is used to configure and enable the SPI system. This register is used to enable the SPI interface, select the device as a master or slave, and determine the data transfer format and word size. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPI_CTL Register Details
Digital Systems: Hardware Organization and Design 9/22/2018 SPI_CTL Register Details The term “word” refers to a single data transfer of either 8 bits or 16 bits, depending on the word length (SIZE) bit in SPI_CTL. There are two special bits which can also be modified by the hardware: SPE and MSTR. The TIMOD field is used to specify the action that initiates transfers to/from the receive/transmit buffers. When set to 00, a SPI port transaction is begun when the receive buffer is read. Data from the first read will need to be discarded since the read is needed to initiate the first SPI port transaction. When set to 01, the transaction is initiated when the transmit buffer is written. A value of 10 selects DMA Receive Mode and the first transaction is initiated by enabling the SPI for DMA Receive mode. Subsequent individual transactions are initiated by a DMA read of the SPI_RDBR. A value of 11 selects DMA Transmit Mode and the transaction is initiated by a DMA write of the SPI_TDBR. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/22/2018 SPI_CTL Register Details The PSSE bit is used to enable the SPISS input for master. When not used, SPISS can be disabled, freeing up a chip pin as general-purpose I/O. The EMISO bit enables the MISO pin as an output. This is needed in an environment where the master wishes to transmit to various slaves at one time (broadcast). Only one slave is allowed to transmit data back to the master. Except for the slave from whom the master wishes to receive, all other slaves should have this bit cleared. The SPE and MSTR bits can be modified by hardware when the MODF bit of the Status register is set. See “Mode Fault Error” on page of ADSP-BF533 Blackfin Processor Hardware Reference manual. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/22/2018 SPI_CTL Register Details *pSPI_CTL = TIMOD_DMA_TX | SIZE | MSTR TIMOD_DMA_TX 0x0003 = 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Summary of SPI Register Functions
Digital Systems: Hardware Organization and Design 9/22/2018 Summary of SPI Register Functions 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

BF533 Direct Memory Access - DMA
Digital Systems: Hardware Organization and Design 9/22/2018 BF533 Direct Memory Access - DMA BF533 DMA Support Architecture of a Respresentative 32 Bit Processor

Processor Memory Architecture
Digital Systems: Hardware Organization and Design 9/22/2018 Processor Memory Architecture 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 BF533 DMA Support The processor has multiple, independent DMA controllers that support automated data transfers with minimal overhead for the core. DMA transfers can occur between the internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the SPORTs, SPI port, UART, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel. The DMA controller supports both one-dimensional (1D) and two-dimensional (2D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to +/- 32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved datastreams. This feature is especially useful in video applications where data can be de-interleaved on the fly. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Generic Names of the DMA Memory-Mapped Registers
Digital Systems: Hardware Organization and Design 9/22/2018 Generic Names of the DMA Memory-Mapped Registers 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 DMA Configuration Architecture of a Respresentative 32 Bit Processor

9/22/2018 Initialize.c: Init1836() // Set up DMA5 to transmit // Map DMA5 to SPI *pDMA5_PERIPHERAL_MAP = 0x5000; // Configure DMA5 // 16-bit transfers *pDMA5_CONFIG = WDSIZE_16; // Start address of data buffer *pDMA5_START_ADDR = sCodec1836TxRegs; // DMA inner loop count *pDMA5_X_COUNT = CODEC_1836_REGS_LENGTH; // Inner loop address increment *pDMA5_X_MODIFY = 2; // enable DMAs *pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN); // enable spi *pSPI_CTL = (*pSPI_CTL | SPE); // wait until dma transfers for spi are finished for (j=0; j<0xaff; j++); // disable spi *pSPI_CTL = 0x0000; } 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

DMA Channel’s Peripheral Map Register
Digital Systems: Hardware Organization and Design 9/22/2018 DMA Channel’s Peripheral Map Register Each DMA channel’s Peripheral Map register (DMAx_PERIPHERAL_MAP) contains bits that: Map the channel to a specific peripheral. Identify whether the channel is a Peripheral DMA channel or a Memory DMA channel. *pDMA5_PERIPHERAL_MAP = 0x5000; 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

DMA Configuration Register
Digital Systems: Hardware Organization and Design 9/22/2018 DMA Configuration Register The DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in Figure 9-3 of ADSP-BF533 Blackfin Processor Hardware Reference, also in this slide is used to set up DMA parameters and operating modes. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

DMA Start Address Register
Digital Systems: Hardware Organization and Design 9/22/2018 DMA Start Address Register The Start Address register (DMAx_START_ADDR/MDMA_yy_START_ADDR), shown in Figure 9-2 of ADSP-BF533 Blackfin Processor Hardware Reference, also in the next slide, contains the start address of the data buffer currently targeted for DMA. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 DMA Count Register For 1D DMA, it specifies the number of elements to read in. For 2D DMA details, see “Two-Dimensional DMA” on page 9-45 of ADSP-BF533 Blackfin Processor Hardware Reference. A value of 0 in X_COUNT corresponds to 65,536 elements. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 DMAx Modify Register The Inner Loop Address Increment register (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) contains a signed, two’s-complement byte-address increment. In 1D DMA, this increment is the stride that is applied after transferring each element. Note X_MODIFY is specified in bytes, regardless of the DMA transfer size. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

DMA Configuration Register
Digital Systems: Hardware Organization and Design 9/22/2018 DMA Configuration Register *pDMA5_CONFIG = WDSIZE_16 = 0x0004; *pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN); DMAEN = 0x0001 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Digital Systems: Hardware Organization and Design 9/22/2018 SPI_CTL Register Details *pSPI_CTL = TIMOD_DMA_TX | SIZE | MSTR TIMOD_DMA_TX 0x0003 = *pSPI_CTL = *pSPI_CTL | SPE SPE 0x4000 = 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

Serial Port Controllers: SPORT
Digital Systems: Hardware Organization and Design 9/22/2018 Serial Port Controllers: SPORT Architecture of a Respresentative 32 Bit Processor

Serial Port Controllers (SPORT)
Digital Systems: Hardware Organization and Design 9/22/2018 Serial Port Controllers (SPORT) The processor has two identical synchronous serial ports, or SPORTs. These support a variety of serial data communications protocols and can provide a direct interconnection between processors in a multiprocessor system. The serial ports (SPORT0 and SPORT1) provide an I/O interface to a wide variety of peripheral serial devices. SPORTs provide synchronous serial data transfer only; The processor provides asynchronous RS-232 data transfer via the UART. Each SPORT has one group of pins: primary data, secondary data, clock, and frame sync for transmit and a second set of pins for receive. The receive and transmit functions are programmed separately. Each SPORT is a full duplex device, capable of simultaneous data transfer in both directions. The SPORTs can be programmed for bit rate, frame sync, and number of bits per word by writing to memory-mapped registers. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 SPORT (cont.) Both SPORTs have the same capabilities and are programmed in the same way. Each SPORT has its own set of control registers and data buffers. The SPORTs use frame sync pulses to indicate the beginning of each word or packet, and the bit clock marks the beginning of each data bit. External bit clock and frame sync are available for the TX and RX buffers. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 SPORT (cont.) With a range of clock and frame synchronization options, the SPORTs allow a variety of serial communication protocols. The SPORTs can operate at up to an SCLK/2 clock rate with an externally generated clock, or 1/2 the system clock rate for an internally generated serial port clock. The SPORT external clock must always be less than the SCLK frequency. Independent transmit and receive clocks provide greater flexibility for serial communications. SPORT clocks and frame syncs can be internally generated by the system or received from an external source. The SPORTs can operate with a transmission format of LSB first or MSB first, with word lengths selectable from 3 to 32 bits. They offer selectable transmit modes and optional μ-law or A-law companding in hardware. SPORT data can be automatically transferred between on-chip and off-chip memories using DMA block transfers. Additionally, each of the SPORTs offers a TDM (Time-Division-Multiplexed) Multichannel mode. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORT Features for Audio Exercise
Digital Systems: Hardware Organization and Design 9/22/2018 SPORT Features for Audio Exercise Provides Direct Memory Access transfer to and from memory under DMA Master control. DMA can be autobuffer-based (a repeated, identical range of transfers) or descriptor-based (individual or repeated ranges of transfers with differing DMA parameters). Executes DMA transfers to and from on-chip memory. Each SPORT can automatically receive and transmit an entire block of data. Permits chaining of DMA operations for multiple data blocks. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 SPORT Pins 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 SPORT Data to be transmitted is written from an internal processor register to the SPORT’s SPORTx_TX register via the peripheral bus. This data is optionally compressed by the hardware and automatically transferred to the TX Shift register. The bits in the Shift register are shifted out on the SPORT’s DTxPRI/DTxSEC pin, MSB first or LSB first, Synchronous to the serial clock on the TSCLKx pin. The receive portion of the SPORT accepts data from the DRxPRI/DRxSEC pin synchronous to the serial clock on the RSCLKx pin. When an entire word is received, the data is optionally expanded, then automatically transferred to the SPORT’s SPORTx_RX register, and then into the RX FIFO where it is available to the processor. A SPORT Receives serial data on its DRxPRI and DRxSEC inputs and Transmits serial data on its DTxPRI and DTxSEC outputs. It can receive and transmit simultaneously for full-duplex operation. For transmit: The data bits (DTxPRI and DTxSEC) are synchronous to the transmit clock (TSCLKx). For receive: The data bits (DRxPRI and DRxSEC) are synchronous to the receive clock (RSCLKx). The serial clock is an output if the processor generates it, or an input if the clock is externally generated. Frame synchronization signals RFSx and TFSx are used to indicate the start of a serial data word or stream of serial words. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORT Generic Operation
Digital Systems: Hardware Organization and Design 9/22/2018 SPORT Generic Operation Writing to a SPORT’s SPORTx_TX register readies the SPORT for transmission. The TFS signal initiates the transmission of serial data. Once transmission has begun, each value written to the SPORTx_TX register is transferred through the FIFO to the internal Transmit Shift register. The bits are then sent, beginning with either the MSB or the LSB as specified in the SPORTx_TCR1 register. Each bit is shifted out on the driving edge of TSCLKx. The driving edge of TSCLKx can be configured to be rising or falling. The SPORT generates the transmit interrupt or requests a DMA transfer as long as there is space in the TX FIFO. As a SPORT receives bits, they accumulate in an internal receive register. When a complete word has been received, it is written to the SPORT FIFO register and the receive interrupt for that SPORT is generated or A DMA transfer is initiated. Interrupts are generated differently if DMA block transfers are performed. For information about DMA, see Chapter 9, “Direct Memory Access.” 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 AD1836 and SPORT 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 // // // Function: Init_Sport // // // // Description: Configure Sport0 for TDM mode, to transmit/receive data // // to/from the AD1836. Configure Sport for external clocks and // // frame syncs // void Init_Sport0(void) { // Sport0 receive configuration // External CLK, External Frame sync, MSB first // 32-bit data *pSPORT0_RCR1 = RFSR; *pSPORT0_RCR2 = SLEN_32; // Sport0 transmit configuration // 24-bit data *pSPORT0_TCR1 = TFSR; *pSPORT0_TCR2 = SLEN_32; // Enable MCM 8 transmit & receive channels *pSPORT0_MTCS0 = 0x000000FF; *pSPORT0_MRCS0 = 0x000000FF; // Set MCM configuration register and enable MCM mode *pSPORT0_MCMC1 = 0x0000; *pSPORT0_MCMC2 = 0x101c; } 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORTx_RCR1 and SPORTx_RCR2 Registers
Digital Systems: Hardware Organization and Design 9/22/2018 SPORTx_RCR1 and SPORTx_RCR2 Registers The main control registers for the receive portion of each SPORT are the Receive Configuration registers: SPORTx_RCR1 and SPORTx_RCR2. A SPORT is enabled for receive if Bit 0 (RSPEN) of the Receive Configuration 1 register is set to 1. This bit is cleared during either a hard reset or a soft reset, disabling all SPORT reception. When the SPORT is enabled to receive (RSPEN set), corresponding SPORT Configuration register writes are not allowed except for SPORTx_RCLKDIV and Multichannel Mode Channel Select registers. Writes to disallowed registers have no effect. While the SPORT is enabled,`SPORTx_RCR1 is not written except for bit 0 (RSPEN). For example: write (SPORTx_RCR1, 0x0001) ; /* SPORT RX Enabled */ write (SPORTx_RCR1, 0xFF01) ; /* ignored, no effect */ write (SPORTx_RCR1, 0xFFF0) ; /* SPORT disabled, SPORTx_RCR1 still equal to 0x0000 */ 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORTx Receive Configuration 1 Register
Digital Systems: Hardware Organization and Design 9/22/2018 SPORTx Receive Configuration 1 Register *pSPORT0_RCR1 = RFSR; RFSR = 0x000; 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORTx Receive Configuration 2 Register
Digital Systems: Hardware Organization and Design 9/22/2018 SPORTx Receive Configuration 2 Register *pSPORT0_RCR2 = SLEN_32; 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORTx_RCR1 and SPORTxRCR2 Registers
Digital Systems: Hardware Organization and Design 9/22/2018 SPORTx_RCR1 and SPORTxRCR2 Registers Additional information for the SPORTx_RCR1 and SPORTxRCR2 Receive Configuration register bits: Receive Enable (RSPEN). This bit selects whether the SPORT is enabled to receive (if set) or disabled (if cleared). Setting the RSPEN bit turns on the SPORT and causes it to sample data from the data receive pins as well as the receive bit clock and Receive Frame Sync pins if so programmed. Setting RSPEN enables the SPORTx receiver, which can generate a SPORTx RX interrupt. For this reason, the code should initialize the ISR and the DMA control registers, and should be ready to service RX interrupts before setting RSPEN. Setting RSPEN also generates DMA requests if DMA is enabled and data is received. Set all DMA control registers before setting RSPEN. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORTx_RCR1 and SPORTxRCR2 Registers
Digital Systems: Hardware Organization and Design 9/22/2018 SPORTx_RCR1 and SPORTxRCR2 Registers Clearing RSPEN causes the SPORT to stop receiving data; it also shuts down the internal SPORT receive circuitry. In low power applications, battery life can be extended by clearing RSPEN whenever the SPORT is not in use. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORTx_TCR1 and SPORTx_TCR2 Registers
Digital Systems: Hardware Organization and Design 9/22/2018 SPORTx_TCR1 and SPORTx_TCR2 Registers The main control registers for the transmit portion of each SPORT are the Transmit Configuration registers, SPORTx_TCR1 and SPORTx_TCR2. A SPORT is enabled for transmit if Bit 0 (TSPEN) of the Transmit Configuration 1 register is set to 1. This bit is cleared during either a hard reset or a soft reset, disabling all SPORT transmission. When the SPORT is enabled to transmit (TSPEN set), corresponding SPORT Configuration register writes are not allowed except for SPORTx_TCLKDIV and Multichannel Mode Channel Select registers. Writes to disallowed registers have no effect. While the SPORT is enabled, SPORTx_TCR1 is not written except for bit 0 (TSPEN). For example: write (SPORTx_TCR1, 0x0001) ; /* SPORT TX Enabled */ write (SPORTx_TCR1, 0xFF01) ; /* ignored, no effect */ write (SPORTx_TCR1, 0xFFF0) ; /* SPORT disabled, SPORTx_TCR1 still equal to 0x0000 */ 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORTX Transmit Configuration 1 Register: SPORTx_TCR1
Digital Systems: Hardware Organization and Design 9/22/2018 SPORTX Transmit Configuration 1 Register: SPORTx_TCR1 *pSPORT0_TCR1 = TFSR; TFSR = 0x000; 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORTX Transmit Configuration 2 Register: SPORTx_TCR2
Digital Systems: Hardware Organization and Design 9/22/2018 SPORTX Transmit Configuration 2 Register: SPORTx_TCR2 *pSPORT0_TCR2 = SLEN_32; 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORTs Multichannel Operation
Digital Systems: Hardware Organization and Design 9/22/2018 SPORTs Multichannel Operation SPORTx_MTCSn Registers The Multichannel Selection registers are used to enable and disable individual channels. The four SPORTx Multichannel Transmit Select registers (SPORTx_MTCSn) specify the active transmit channels. There are four registers, each with 32 bits, corresponding to the 128 channels. Setting a bit enables that channel so that the serial port selects that word for transmit from the multiple word block of data. For example, setting bit 0 selects word 0, setting bit 12 selects word 12, and so on. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORTs Multichannel Operation
Digital Systems: Hardware Organization and Design 9/22/2018 SPORTs Multichannel Operation Setting a particular bit in a SPORTx_MTCSn register causes the serial port to transmit the word in that channel’s position of the datastream. Clearing the bit in the SPORTx_MTCSn register causes the serial port’s data transmit pin to three-state during the time slot of that channel. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 SPORTx_MRCSn Registers The Multichannel Selection registers are used to enable and disable individual channels. The SPORTx Multichannel Receive Select registers (SPORTx_MRCSn) specify the active receive channels. There are four registers, each with 32 bits, corresponding to the 128 channels. Setting a bit enables that channel so that the serial port selects that word for receive from the multiple word block of data. For example, setting bit 0 selects word 0, setting bit 12 selects word 12, and so on. 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORTx Multichannel Transmit Select Registers
Digital Systems: Hardware Organization and Design 9/22/2018 SPORTx Multichannel Transmit Select Registers *pSPORT0_MTCS0 = 0x000000FF; 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

SPORTx Multichannel Receive Select Registers
Digital Systems: Hardware Organization and Design 9/22/2018 SPORTx Multichannel Receive Select Registers *pSPORT0_MRCS0 = 0x000000FF; 22 September 2018 Veton Këpuska Architecture of a Respresentative 32 Bit Processor

9/22/2018 Architecture of a Respresentative 32 Bit Processor

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