1. Multilevel Full-Chip Routing for the X-Based Architecture
Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, and Sao-Jie Chen
Graduate Institute of Electronics Engineering
Department of Electrical Engineering
National Taiwan University
Taipei, Taiwan

2. Multilevel X Routing Framework
Agenda
Introduction
Trapezoid-Shaped
Track Assignment
Routability-Driven
Pattern Routing
X-Architecture
Steiner Tree
Multilevel X Routing Framework
Experimental Results
Conclusions

3. Wiring Dominates Nanometer Design
As integrated circuit geometries keep shrinking, interconnect delay has become the dominant factor in determining circuit performance.
For 90 nm technology,
interconnect delay
will account for
75% of the overall delay.
Source: Cadence Design System

4. Solutions Timing optimization techniques: New IC technologies:
Wire sizing
Buffer insertion
Gate sizing
X-architecture
Manhattan-architecture L
New IC technologies:
Copper and low-k dielectrics
X-architecture
The X-architecture is a new interconnect architecture based on the pervasive use of diagonal routing in chips, and it can shorten interconnect length and thus circuit delay.

5. Manhattan- vs. X-Architecture
Source: Cadence

6. X-Architecture X-initiative At least 42 members.
Veritable supply chain from IP and design implementation to photomask and manufacturing.
TC90400XBG (Digital TV) by Toshiba
Impacts on EDA tools:
Placement and Routing
Extraction

7. Routing Trends
Billions of transistors may be fabricated in a single chip for nanometer technology.
Need tools for very large-scale designs.
Framework evolution for CAD tools:
Flat
Hierarchical
Multilevel
Source: Intel at ISSCC-03

8. Two-Stage Routing Global Routing Detailed Routing Global routing
Partition the routing area into tiles.
Find tile-to-tile paths for all nets.
Attempt to optimize given objectives.
Detailed routing
Assign actual tracks and vias for nets.
tile
Global Routing
Detailed Routing

9. Flat Routing Framework
Flat Framework
Sequential approaches
Maze searching
Line searching
Concurrent approaches
Network-flow based algorithms
Linear assignment formulation
Drawback: hard to handle larger problems
Sequential
Concurrent

10. Hierarchical Routing Framework
Hierarchical Framework
Top-down: divide and conquer
Drawback: lack the global information for the interaction
among subregions ? …

11. Multilevel Framework
It has been successfully applied to partitioning, floorplanning, placement and routing in VLSI physical design and many more.
Ingredients:
Bottom-up Coarsening: Iteratively groups a set of circuit components and collects global information.
Top-down Uncoarsening: Iteratively ungroups clustered components and refines the solution.
coarsening
uncoarsening

12. Previous Multilevel Routing Frameworks
Multilevel full-chip routing frameworks have attracted much attention recently.
Cong et al., “Multilevel approach to full-chip gridless routing,” ICCAD 2001.
Lin and Chang, “A novel framework for multilevel routing considering routability and performance,” ICCAD 2002.
Ho et al., “A fast crosstalk- and performance-driven multilevel routing system,” ICCAD 2003.
Ho et al., “Multilevel Routing with Antenna Avoidance,” ISPD 2004.
Manhattan-based multilevel routers

13. Multilevel Full-Chip Router
Our X-Multilevel Routing Framework
Coarsening
Uncoarsening
Perform congestion-driven pattern routing for local connections and then estimate routing congestion for the next level.
Use point-to-path maze routing to reroute failed nets level by level.
To-be-routed net
Already-routed net G0 G1 G2 G3
The 1st X-Based
Multilevel Full-Chip Router
Perform trapezoid-shaped track assignment for long segments on trapezoid panels, and short segments are routed by a point-to-path maze router.

14. Perform track assignment for longer and diagonal segments
Benefits of Track Assignment
Good for run-time reduction
Effective for wirelength minimization n
Wirelength: 5
Wirelength: 1+2
Metal 1
Metal 2
Metal 3
Metal 4
Manhattan-Architecture
X-Architecture
# Vias: 1 (VIA12)
# Vias: 3 (VIA12, VIA23, and VIA34)
<
>
Perform track assignment for longer and diagonal segments

15. Multilevel X Routing Framework
Agenda
Introduction
X-Architecture
Steiner Tree
Multilevel X Routing Framework
Routability-Driven
Pattern Routing
Trapezoid-Shaped
Track Assignment
Experimental Results
Conclusions

16. Research on Octilinear Steiner Trees
Related work:
C. S. Coulston, “Constructing exact octagonal Steiner minimal trees,” GLSVLSI 2003.
A. B. Kahng et al., “High scalable algorithms for rectilinear and octilinear Steiner trees,” ASPDAC 2003.
Q. Zhu et al., “Efficient octilinear Steiner tree construction based on spanning graphs,” ASPDAC 2004.
For the previous approaches, those with relatively better quality may not achieve good efficiency.
Our work:
Optimal Routing for
3-Terminal Nets
on the X-Architecture
X-Steiner Tree Algorithm
Based on
Delaunay Triangulation

17. Optimal 2-Terminal Net Routing Based on X-Architecture1 2 1 2

18. Optimal 3-Terminal Net Routing Based on X-Architecture1 1 1 3 ? 3 2 2 2
Bounding box of 900 and 1800 segments
Bounding box of 450 and 1350 segments
Merged Region
Lemma:
The optimal routing solution of a 3-terminal net, of which one
terminal is located in the merged region of the other two
terminals, is the Octilinear Minimum Spanning Tree (OMST) of it.

19. Optimal 3-Terminal Net Routing: Case I
If the 3rd terminal is in region R4 (R4’)… 1 a b 2 R4
R3’
R2’
R1’ 2 3 1
The optimal 3-terminal net routing is the OMST of these three points.

20. Optimal 3-Terminal Net Routing: Case II
If the 3rd terminal is in region R2 (R2’)… 3 R1 R2 R3
R4’ 1 a b 2 R4
R3’
R2’
R1’ 1 2 a 3
The optimal 3-terminal net routing is the OMST of these three points and Steiner point a (b).

21. Optimal 3-Terminal Net Routing: Case III
If the 3rd terminal is in region R1 (R1’, R3, or R3’)…
R1a
R1b R2 S V 1 2 3 S R2 R3
R4’ 1 2 R4
R3’
R2’
R1’
The optimal 3-terminal net routing is the OMST of these three points and Steiner point S.

22. 3-Terminal Net Routing on X-Architecture (X3TR)
Theorem:
The X3TR algorithm finds the optimal routing of the minimum wirelength for a 3-terminal net on the X-architecture in constant time.

23. X-Steiner Tree Algorithm Based on Delaunay Triangulation
7.6
13.8
8.4
12.6
7.0
9.8
9.6
12.6
8.6
7.4
11.8
8.6
10.6
13.4
(a)
(b)
(c)
Delaunay triangulation
Compute optimal wirelength of OMST for each triangle and sort them
Run X3TR for triangles in increasing order

24. Local Refinement for Wirelength2
4 < ≈ 4.2

25. X-Steiner Tree Algorithm Based on Delaunay Triangulation
7.6
13.8
8.4
12.6
7.0
9.8
9.6
12.6
8.6
7.4
11.8
8.6
10.6
13.4
(a)
(b)
(c)
Delaunay triangulation
Compute optimal wirelength of OMST for each triangle and sort them
O(n lg n)

26. Multilevel X Routing Framework
Agenda
Introduction
X-Architecture
Steiner Tree
Multilevel X Routing Framework
Routability-Driven
Pattern Routing
Trapezoid-Shaped
Track Assignment
Experimental Results
Conclusions

27. Multilevel Routing Graph
Multilevel X Routing Model
tile
Metal 1
Metal 2
Metal 3
Metal 4
Partitioned Layout
Multilevel Routing Graph

28. Global Pattern Routing: 1-Bend
1-Bend Pattern routing m m n n
(a)
(b)

29. Global Pattern Routing: 2-Bend
2-Bend Pattern routing m m n n
(c)
(d)
Shortest path length:

30. Cost Function in Global Pattern Routing
Gi = (Vi , Ei) : multilevel routing graph at level i.
Define
Then
where Ce is the congestion of edge e
and
where pe and de are the capacity and density associated with e, respectively.

31. Multilevel X Routing Framework
Agenda
Introduction
X-Architecture
Steiner Tree
Multilevel X Routing Framework
Routability-Driven
Pattern Routing
Trapezoid-Shaped
Track Assignment
Experimental Results
Conclusions

32. Trapezoid-Shaped Track Assignment
Trapezoid-Shaped Track Assignment Problem:
Input:
a set of segments S
a set of tracks T in a trapezoid panel
a cost function F : S x T → N, which represents the cost of assigning a segment to a track
Objective:
find an assignment that minimizes the sum of the costs.
Trapezoid panel
Zoom in
Bottom-up fashion

33. Wire Pitch for X-Routing
How to connect HV and diagonal tracks? 
Pitch for HV tracks 
Virtual track
Pessimistic track
Aligned track
DRC-violated track
()

34. Connect to the Grid Point
Wrong-way jog
Diamond-shaped global cell
45o
135o
<
Detour!

35. Trapezoid Shape Track Assignment
Middle Zone
Right Zone
Left Zone g f e d c b
Obstacles a 1
Left Segments 2 3
Middle Segments 4
Right Segments
Trapezoid Panel

36. Our X-Multilevel Routing Framework Recap
Coarsening
Uncoarsening
Perform congestion-driven pattern routing for local connections and then estimate routing congestion for the next level.
Use point-to-path maze routing to reroute failed nets level by level.
To-be-routed net
Already-routed net G0 G1 G2 G3
Perform trapezoid-shaped track assignment for long segments on trapezoid panels, and short segments are routed by a point-to-path maze router.

37. Multilevel X Routing Framework
Agenda
Introduction
X-Architecture
Steiner Tree
Multilevel X Routing Framework
Routability-Driven
Pattern Routing
Trapezoid-Shaped
Track Assignment
Experimental Results
Conclusions

38. Experimental Setting Language: C++ Library: STL, LEDA, LayoutDB (UCLA)
Platform: 1GHz Sun Blade 2000 with 1GB memory
Benchmarks:
Circuits
Size (μm)
#Layer
#Nets
#Pins
S5378
4330x2370 3
3124
4734
S9234
4020x2230
2774
4185
S13207
6590x3640
6995
10562
S15850
7040x3880
8321
12566
S38417
11430x6180
21035
32210
S38584
12940x6710
28177
42589

39. Experimental Results
Compared with the Manhattan-based multilevel router, our X-router reduced
wirelength by 18.7%
, average delay by 8.8%
, and run-time by 13%.
Circuits
Results of ICCAD ‘03†
Our Results
Wirelength
#Vias
Cmp. Rates
Davg
Run-Time
S5378
8.4e7
7451
99.8%
1258
10.6
7.2e7
7432
1119
10.5
S9234
6.0e7
6239
99.9%
1009
8.1
5.5e7
6323
956
7.9
S13207
2.3e8
16003
1243
22.6
1.8e8
15897
1074
20.9
S15850
2.9e8
19126
99.7%
1253
62.6
2.2e8
18999
99.4%
1178
54.1
S38417
8.0e8
49816
1146
71.3
6.1e8
49131
99.0%
1034
59.8
S38584
1.1e9
65798
1151
255.6
8.8e8
65018
99.1%
1068
198.1
Comp.
1.19
1.00
1.09
1.13 1
18.7%
8.8%
13.0%
Davg: Average delay (Elmore delay model)
ICCAD 2003:
T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D. T. Lee,
“A fast crosstalk- and performance-driven multilevel routing system.”

40. X Routing Results of S38417

41. Multilevel X Routing Framework
Agenda
Introduction
X-Architecture
Steiner Tree
Multilevel X Routing Framework
Routability-Driven
Pattern Routing
Trapezoid-Shaped
Track Assignment
Experimental Results
Conclusions

42. Conclusions We propose the first X-based multilevel full-chip router.
Optimal routing for 3-terminal nets on the X-architecture in constant time
General X-Steiner tree algorithm based on delaunay triangulation
Virtual tracks for effective diagonal routing resource usage
The experimental results have shown that our approach reduced wirelength by 18.7% and average delay by 8.8% with similar routing completion rates and via counts.
Our future work lies in an integrated multilevel placement and routing system for the X-architecture.

43. Acknowledgements
Thank Dr. Cliff Hou, Dr. LC Lu, and Mr. Ken Wang of TSMC for their helpful discussions.
This work was partially supported by grants from UMC and NSC, Taiwan.

44. Thank You!!
This concludes my talk.
Thank you for your attention. 30