1. High Performance Interconnect and Packaging
Chung-Kuan Cheng
CSE Department
UC San Diego

2. Research Scope Scalable System: Power, Delay, Cost, Reliability
Interconnect-Driven Designs
Wire Planning: Non-Manhattan Interconnect
Networks: Topology, Physical Layout
Clock & Power: Shunts + Trees (3)
Interconnect Style: Surfliner (2)
Datapath: Shifters, Adders, Mul. Div.
Packaging: Pin Breakaway (1)
Simulation
Static Timing Analysis: Hierarchy, Incremental
SPICE: Whole System Analysis

3. 1. Pin Breakaway Interfaces of Chip and Package, Package and Board.
Breakaway of Array of Pins
Patterns of Breakaway
Obj: Cost= # Breakaway Layers

4. 1. Pin Breakaway Row by Row Escape:
Escape interconnect row by row from outside toward inside.

5. 1. Pin Breakaway (Cont.) Parallel Triangular Escape:
This method divides the objects into groups and escape each group with a triangular outline.

6. 1. Pin Breakaway (Cont.) Central Triangular Escape:
Escape objects from the center of the outside row and expands the indent with a single triangular outline.

7. 1. Pin Breakaway (Cont.) Two-Sided Escape:
Escape objects from the inside as well as from the outside. The outline shrinks slowly and also follow zigzag shape.

8. The movement of area array contour
1. Pin Breakaway (Cont.)
Row by Row Parallel Triangles Central Triangle Two-Sided
The movement of area array contour

9. 1. Pin Breakaway: Design Rules
Parameters used:
the pad pitch = 150m
the pad diameter = 75m
the line width = 20m
the spacing = 20m

10. 1. Pin Breakaway: Results
40 x 40
Layer
Row by row
Parallel triangular
Central triangular
Two sided 1
304
276
100
312 2
272
340
156
328 3
240
292
228
308 4
208
300
324 5
176
164
372 6
144
124
444 7
112 8 80 9 48 10 16

11. 1. Pin Breakaway: Results
20 x 20
Layer
Row by row
Parallel triangular
Central triangular
Two sided 1
144
132 92
140 2
112
116
160 3 80 96
100 4 48 28 52 5 16

28. 2. Interconnect Style: Surfliner
Global Interconnect trend
Scalability

29. 2. Surfliner - Features Speed of light Low Power Consumption
< 1/5 Delay of Traditional Wires
Low Power Consumption
< 1/5 Power Consumption
Robust against process variations
Short Latency
Insensitive to Feature Size
Differential Signaling
Shield for low swing signals

30. 2. Surfliner:Transmission Line Model
Differential Lossy Transmission Line
Surfliner
Shunt conductance G= 0 for wires of IC
Add shunt conductance G= RC/L
Flat response from DC to Giga Hz
Telegraph Cable: O. Heaviside in 1887.

31. 2. Surfliner: Distortionless Line
Telegrapher’s equation:
Propagation Constant:
Wave Propagation:
Alpha and Beta corresponds to speed and phase velocity.

32. 2. Surfliner: Distortionless Lines
Set G=RC/L
Attenuation and Beta
Characteristic impedance: (pure resistive)
Phase Velocity (Speed of light in the media)
Attenuation:

33. 2. Surfliner: Distortionless Lines

34. 2. Surfliner: Performance
Speed of Light: 5ps/mm or 50ps/cm
Power: 10mW at GHz
Conductance variation = 10%, f=10MHz~10GHz
Attenuation and velocity variation < 1%

35. 2. Surfliner: Implementation
Add shunt conductance
Resistors realized by serpentine unsilicided poly, diffusion resistors, or high resistive metal

36. 2. Surfliner: Simulation Results
Characteristic Impedance (at 10GHz) : Ohm
Inductance: 0.22nH/mm Capacitance: 141fF/mm
Attenuation: 253mv magnitude at receiver’s end (assuming 1V at sender’s end)
Using Microstrip (free space above the wires): impedance can be improved to 52.8Ohm

37. 2. Surfliner: Settings
Agilent ADS Momentum extract 4-port S-parameters
HSpice: Transient analysis
Assume 1023 bit pseudo random bit sequence (PRBS)
15GHz clock
10% of clock period transition slope for each rising and falling edge

38. 2. Surfliner: Simulation Results
120 Stages
4 Stages

39. 2. Surfliner: Simulation
Jitter and silicon area usage
#Stages 4 10 20 40 80
120
160
Jitter (ps) 27
9.5
5.4
4.2
3.9
2.1
2.08
Area (um2)
0.52
3.25 13 52
208
468
832
Power w/ different width and separation
(w, s) (um)
(3,3)
(4,4)
(5,4)
(10,5)
Power (mW)
4.98
3.62
3.02
2.13
Attenuation
0.307
0.415
0.496
0.60

40. 2. Applications of Surfliner
1.Clock distributions
2. Data communications: Buses Between CPUs, DSPs, Memory Banks

41. 2. Application of Surfliner
3. High Performance Low Power Wafer Packaging

42. 2. Surfliner: Current Status
What we have done
Derived a conservative design
Performed simulation
We are looking forward to
Design and fabricate the test chip
Explore architectures to exploit the advantages of Surfliner

43. 3. Clock Distribution: Shunts + Trees
3.1 RC Shunts
3.2 Inductive Effects
Contribution:
Analytical skew expression
Formulation of Multilevel Optimization
Empirical Observation

44. 3. Clock: Linear Variations Model
Process variation model
Transistor length
Wire width
Linear variation model
Power variation model
Supply voltage varies randomly (10%)

45. 3.1 Clock: RC Model Input: an n level meshes and h-trees
Constraint: routing area, parameter variations
Objective: skew

46. Simplified Circuit Model

47. Transient Response when t<T
VS1=u(t)
Vs2=0
Let
Then
V1 = A + B
V2 = A - B

48. Skew Expression Assumptions: T<<RsC Rs /R <<RsC/T
Using first order
Taylor’s expansion

49. Spice Validation of Skew Function

50. Skew on mesh
Conjectured skew expression
Using regression to get k

51. K values for n by n meshes

52. Optimization
Skew function
Multi level skew function

53. Experimental Settings
Die size 1cm by 1cm
100nm copper technology
Ground Shielded Differential Signal Wires for Global Clock Distribution
Routing area is normalized to the area of a 16 by 16 mesh with minimal wire width + -
GND

54. Experimental Results
Optimized wire width

55. Optimal Routing Resources Allocation
level-1
level-2
level-3
level-4
total area

56. Skew reduction V.S. Mesh Area

57. Experiments—Optimized Skew

58. Robustness Against Supply Voltage Variations

59. 3.2 Clock: RLC Model
Motivation: RLC shunt effect diminishes in multiple-GHz range
Model of Transmission line
Formulation of Multilevel Optimization
Empirical Observation

60. 3.2 Motivation: Inductance Diminishes Shunt Effects
0.5um wide 1.2 cm long copper wire
Input skew 20ps
f(GHz)
0.5 1
1.5 2 3
3.5 4 5
skew(ps)
3.9
4.2
5.8
7.5
9.9 13 17 26

61. 3.2 Motivation: Synchronization at wavelength distance

62. 3.2 Motivation: Multilevel Transmission Line Spiral Network

63. 3.2 Model of Transmission Line: Shunt with Two Sources
Transmission Line with exact multiple wave length long
Large driving resistance to increase reflection

64. Spice Validation of Skew Equation

65. 3.2 Model of Transmission Line: Multiple Sources Case
Random model:
Infinity long wire
Input phases uniformly distribution on [0, Φ]

66. Configuration of Wires
Coplanar copper transmission line
height: 240nm, separation: 2um, distance to ground: 3.5um, width(w): 0.5 ~ 40um
Use Fasthenry to extract R,L
Linear R/L~w Relation
R/L = a/w+b

67. 3.2 Formulation of Multilevel Distribution
Min:
S.t.:

68. Experimental Results Set chip size to 2cm x 2cm
Clock frequency GHz
Synthesize H-tree using P-tree algorithm
Set the initial skew at each level using SPICE simulation results under our variation model
Use FastHenry and FastCap to extract R,L,C value
Use W-elements in HSpice to simulate the transmissionlin

69. Optimized Wire Width Total Area W1 (um) W2 (um) W3 (um) Skew M (ps)
Skew S (ps)
Impr.(%)
23.15 0%
0.5
1.7
17.796
20.50
13% 1
1.9308
1.0501
12.838
14.764 3
2.5751
1.3104
1.3294
8.6087
8.7309
15% 5
2.9043
3.7559
2.3295
6.2015
6.3169
16% 10
3.1919
4.5029
6.8651
4.2755
5.2131
18% 15
3.6722
6.1303
10.891
2.4917
3.5182
29% 20
4.0704
7.5001
15.072
1.7070
2.6501
37% 25
4.4040
8.6979
19.359
1.2804
2.1243
40%

70. Simulated Output Voltages
Transient response of 16 nodes on transmission line
Signals synchronized in 10 clock cycles

71. Simulated Output voltages
Steady state response: skew reduced from 8.4ps to 1.2ps

72. Power Consumption Area 3 4 5 7 10 15 20 25 PM(mw) 0.4 0.5 0.7 0.9 1.0
1.4
1.5
1.6
PS(mw)
0.83
2.1
2.64
3.04
4.7
7.2
8.3
reduce(%) 48 67 66 70 79 81
PM: power consumption of multilevel mesh
PS: power consumption of single level mesh

73. Skew with supply fluctuation
Area
Skew-S
Skew-M
Ave.
Worst
Impr(%)
28.4
36.5 0% 3
9.75
12.33
8.75
9.07
11% 5
7.32
9.06
6.55
6.91
12% 10
6.31
805
4.41
5.41
30% 15
5.03
7.33
2.81
4.93
44% 25
3.83
4.61
1.72
3.06
55%

74. 3.2 Future Directions
Exploring innovative topologies of transmission line shunts
Design clock repeaters and generators
Actual layout and fabrication of test chip

75. Conclusion
1 Post Doc., 10 Ph.D. students work on interconnect, packaging, and simulation
Plan to release packages on interconnect planning (topology and design style)
Need help on fabrication and measurement