1. Adaptation Behavior of Pipelined Adaptive Filters
Prakash Khanikar
Varun Gopalakrishna
ECE Spring 2004

2. Adaptive Filters
Coefficients updated at each iteration until they converge
To minimize the difference between filter output and desired signal
Adaptation processes based on minimization criteria
LMS (Least Mean Squares)
RLS (Recursive Least Squares)
ECE Spring 2004

3. Adaptive Filters
LMS update based on instantaneous sample value of the tap input vector and error signal
RLS update based on all past available information
Ensemble averaging (LMS) vs. Time based averaging (RLS)
RLS has a much faster convergence rate than LMS
Attained at the expense of an increase in computational complexity
ECE Spring 2004

4. Pipelining approach
Recursive and adaptive filters difficult to pipeline due to long feedback loops
Look ahead computation could be used but not practical for IC implementations
Substantial hardware saving by use of relaxed look ahead transformation
To reduce computational complexity, there is also a need to investigate systolic arrays
ECE Spring 2004

5. Relaxed Look Ahead
Based on approximating the algorithms obtained via look-ahead
Sacrifice of the equivalence between serial and pipelined algorithms at expense of convergence characteristics
Smaller hardware overhead making attractive for VLSI implementation
Higher throughput with power-area tradeoff
Higher clock speed
ECE Spring 2004

6. Exponentially weighted RLS algorithm
k(n)
d*(n)
z-1 I
uH(n) ∑ +
w(n)
w(n-1)
ECE Spring 2004

7. ECE Spring 2004

8. Stability Issues Stability of the pipelined recursive realizations
Sensitive to the filter coefficients
ECE Spring 2004

9. Systolic array Implementation
Input data is not consumed in traditional pipelining approaches
QRD-RLS algorithm
Good numerical properties
Can be mapped to a coarse grain pipelining systolic array
Highly suitable for VLSI implementation
Systolic architecture based on QRD-RLS algorithm using the Givens rotation
ECE Spring 2004

10. Conclusions
Use of techniques and algorithms like pipelining, systolic array mapping towards efficient implementation of adaptive filters
Faster implementation (higher clock speed) without hardware overhead
Immediate Goals
To exploit inherent parallelism through block/parallel processing techniques
To propose an efficient systolic array architecture for the RLS algorithm
ECE Spring 2004