1. VLSI Testing Lecture 6: Fault Simulation
Dr. Vishwani D. Agrawal
James J. Danaher Professor of Electrical and Computer Engineering
Auburn University, Alabama 36849, USA
IIT Delhi, Aug 20, 2013, 3:30-4:30PM
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

2. Lecture 6:Fault Simulation
Contents
Problem and motivation
Fault simulation algorithms
Serial
Parallel
Concurrent
Random Fault Sampling
Summary
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

3. Problem and Motivation
Fault simulation Problem:
Given
A circuit
A sequence of test vectors
A fault model
Determine
Fault coverage - fraction (or percentage) of modeled faults detected by test vectors
Set of undetected faults
Motivation
Determine test quality and in turn product quality
Find undetected fault targets to improve tests
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

4. Fault simulator in a VLSI Design Process
Verification
input stimuli
Verified design
netlist
Fault simulator
Test vectors
Modeled
fault list
Remove
tested faults
Test
compactor
Delete
vectors
Fault
coverage ?
Low
Test
generator
Add vectors
Adequate
Stop
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

5. Fault Simulation Scenario
Circuit model: mixed-level
Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals
High-level models (memory, etc.) with pin faults
Signal states: logic
Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits
Four states (0, 1, X, Z) for sequential MOS circuits
Timing:
Zero-delay for combinational and synchronous circuits
Mostly unit-delay for circuits with feedback
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

6. Fault Simulation Scenario (Continued)
Mostly single stuck-at faults
Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use
Equivalence fault collapsing of single stuck-at faults
Fault-dropping – a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis
Fault sampling -- a random sample of faults is simulated when the circuit is large
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

7. Fault Simulation Algorithms
Serial
Parallel
Deductive*
Concurrent
Differential*
* Not discussed; see M. L. Bushnell and V. D. Agrawal,
Essentials of Electronic Testing for Digital, Memory
and Mixed-Signal VLSI Circuits, Springer, 2000,
Chapter 5.
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

8. Lecture 6:Fault Simulation
Serial Algorithm
Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list:
Modify netlist by injecting one fault
Simulate modified netlist, vector by vector, comparing responses with saved responses
If response differs, report fault detection and suspend simulation of remaining vectors
Advantages:
Easy to implement; needs only a true-value simulator, less memory
Most faults, including analog faults, can be simulated
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

9. Serial Algorithm (Cont.)
Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits
Alternative: Simulate many faults together
Test vectors
Fault-free circuit
Comparator
f1 detected?
Circuit with fault f1
Comparator
f2 detected?
Circuit with fault f2
Comparator
fn detected?
Circuit with fault fn
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

10. Parallel Fault Simulation
Compiled-code method; best with two-states (0,1)
Exploits inherent bit-parallelism of logic operations on computer words
Storage: one word per line for two-state simulation
Multi-pass simulation: Each pass simulates w-1 new faults, where w is the machine word length
Speed up over serial method ~ w-1
Not suitable for circuits with timing-critical and non-Boolean logic
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

11. Parallel Fault Sim. Example
Bit 0: fault-free circuit
Bit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1
c s-a-0 detected a b e c
s-a-0 g d f
s-a-1
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

12. Concurrent Fault Simulation
Event-driven simulation of fault-free circuit and only those parts of the faulty circuit that differ in signal states from the fault-free circuit.
A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any.
All events of fault-free and all faulty circuits are implicitly simulated.
Faults can be simulated in any modeling style or detail supported in true-value simulation (offers most flexibility.)
Faster than other methods, but uses most memory.
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

13. Lecture 6:Fault Simulation
Conc. Fault Sim. Example a0 b0 c0 e0 1 1 1 1 1 a 1 1 1 e b 1 c 1 1 g 1 a0 b0 c0 e0 d f 1 1 1 1 b0 d0 f1 g0 1 f1 d0 1 1
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Lecture 6:Fault Simulation

14. Lecture 6:Fault Simulation
Fault Sampling
A randomly selected subset (sample) of faults is simulated.
Measured coverage in the sample is used to estimate fault coverage in the entire circuit.
Advantage: Saving in computing resources (CPU time and memory.)
Disadvantage: Limited data on undetected faults.
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

15. Motivation for Sampling
Complexity of fault simulation depends on:
Number of gates
Number of faults
Number of vectors
Complexity of fault simulation with fault sampling depends on:
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Lecture 6:Fault Simulation

16. Lecture 6:Fault Simulation
Random Sampling Model
Detected
fault
Undetected
fault
All faults with
a fixed but
unknown
coverage
Random
picking
Np = total number of faults
(population size)
C = fault coverage (unknown)
Ns = sample size
Ns << Np
c = sample coverage
(a random variable)
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

17. Probability Density of Sample Coverage, c
(x--C )2
─ ──────
s 2
p (x ) = Prob(x < c < x +dx ) = ─────── e
s (2 p) 1/2
C (1 - C)
Variance, s 2 = ────── Ns
Sampling
error s s
p (x )
Mean = C x
C -3s x
C +3s
1.0 C
Sample coverage
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

18. Lecture 6:Fault Simulation
Sampling Error Bounds
C (1 - C )
| x - C | = 3 [ ────── ] 1/2 Ns
Solving the quadratic equation for C, we get the
3-sigma (99.7% confidence) estimate:
4.5
C 3s = x ─── [ Ns x (1 - x )]1/2 Ns
Where Ns is sample size and x is the measured fault
coverage in the sample.
Example: A circuit with 39,096 faults has an actual fault coverage of 87.1%. The measured coverage in a random sample of 1,000 faults is 88.7%. The above formula gives an estimate of 88.7% ± 3%. CPU time for sample simulation was about 10% of that for all faults.
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation

19. Lecture 6:Fault Simulation
Summary
Fault simulator is an essential tool for test development.
Concurrent fault simulation algorithm offers the best choice.
For restricted class of circuits (combinational and synchronous sequential with only Boolean primitives), differential algorithm can provide better speed and memory efficiency.
For large circuits, the accuracy of random fault sampling only depends on the sample size (1,000 to 2,000 faults) and not on the circuit size. The method has significant advantages in reducing CPU time and memory needs of the simulator.
Copyright 2001, Agrawal & Bushnell
Lecture 6:Fault Simulation