1. Formally capturing the structure of bus specifications
Kathi Fisler
WPI Computer Science

2. Basic transfer
Burst operation

3. First two diagrams should compose to yield third
Glitches
… and lack thereof
Periods of instability

4. Compositional Core Protocols
HADDR
HWRITE
HWDATA
HREADY
= Addr
= H
= dc
; dc*
; Data ; dc*
; H ; dc*
Different cycle lengths per concatenation

5. Compositional Core Protocols
HADDR
HWRITE
HWDATA
HREADY
= Addr
= H
= dc
; dc*
; Data ; dc*
; H ; dc*
Core diagram abstracts part of protocol

6. Compositional Core Protocols
HADDR
HWRITE
HWDATA
HREADY
= Addr
= H
= dc
; dc*
; Data ; dc*
; H ; dc*
single logical value
Diagrams in document show implementation, not specification

7. Compositional Core Protocols
HADDR
HWRITE
HWDATA
HREADY
= Addr
= H
= dc
; dc*
; Data ; dc*
single logical value
Must decouple clocking and concatenation
Two-dimensional regular expression

8. Naïve regular expressions elide causality and control
Events trigger diagram blocks
Exploring functional reactive languages (eg FrTime)

9. Each portion builds on earlier protocols and adds complexity
Basic transfer
How do we design a specification language to capture this structure?
Burst operation
Error conditions
Split transfers
Reset transfers