1. Min Cost Network Flow
C.Gebotys, ECE 602

2. Reduce code size in DSP Processor
Load address_register, #value AR<=#value
Load address_register2,#value2 AR2<=#value2
… addresses
Load address_register+, register0 r0<=m[AR] , AR+ 3 …
Load address_register2-, register7 r7<=m[AR2] , AR- 2 ..
Load address_register2, register3 r3<=m[AR2] 1
note: if #value=3, #value2=2, could have optimally used only 1 AR
In the solution

3. Minimize #AR load instructions
Each memory access is represented by an address at a clock cycle.
Assign each memory access to an address register
If two memory accesses are assigned to one address register but the addresses are greater than ‘1’ unit apart, then a cost of one is assigned to that pair (since a post-increment/decrement is not supported. And an extra AR load instruction is required)
Objective: minimize cost ie. Minimize # of AR load instructions

4. Addr1 addr2 addr3 addr4
TIME

5. Network flow
S node
T node

6. Fixed Flow in Network
Flow out of node s must be equal to F.

7. Circulation
S node
T node

8. Flow through all nodes We need to ensure each
Node will have a flow of 1
Through it
Flow=1 on this
arc
THIS Must be a part of all network flow formulations (both fixed flow min cost and
Min cost circulation formulations of the problem)

9. Fix total amount of flow
Total flow = #address registers
Alternatively we can use a circulation graph so that we do not need to fix the amount of flow. The cost of flow can be placed on the arc from t to s in graph