1. CMOS Devices PN junctions and diodes NMOS and PMOS transistors
Resistors
Capacitors
Inductors
Bipolar transistors

2. The MOS Transistors

3. The MOS Transistors

4. CMOS Device Model Objective CMOS transistor models
Hand calculations for analog design
Non-idealities and their effects
Efficient and accurate simulation
CMOS transistor models
Large signal model
Small signal model
Simulation model
Noise model

5. Good for VDS <VGS-VTH
After that, ID become saturated.

7. Linear in deep triode As vDS  0, ron 
Pro: voltage control of resistivity.
Con: nonlinear resistor.

8. MOST Regions of Operation
Cut-off, or non-conducting: vGS <VT
iD=0 approximately
Conducting, or on: vGS >=VT
Saturation: vDS > vGS – VT
Triode or linear or ohmic or non-saturation: vDS <= vGS – VT
Saturation voltage:

9. With channel length modulation

10. iD vs vDS for several VGS
gds
gm*DVGS

11. Influence of Channel Length on l
Lmin = 0.25
Johns and Martin book gives an approximate formula with l  1/L
At >=2*Lmin, l is small, Ro is large
After 1um, l remains about the same

12. Influence of VBS
VBS changes threshold voltage, and hence changes i-v curve.

13. Temperature Dependence of Mobility
Linear Temperature Dependence of threshold voltage
Saturation Velocity
Junction capacitance
Barrier potential
Drain resistance

14. This is nonlinear if Vbs is temperature dependent

17. Referenced from Filanovsky’s paper
0.35um process
ZTC
biasing
Referenced from Filanovsky’s paper

18. Reality: no single point crossing
Not just one single crossing ID
In AMI0.6 process
Test on a single NMOS biased with fixed Vgs and Vds
Vgs

20. To refine the value AMI 0.6 Vgs=1.12V Vgs=1.14V Optimum curve
TC = 41 ppm/C
Vgs=1.17V

21. Generic 018
Vgs=0.717V
Vgs=0.721V
TC=27 ppm/C
Vgs=0.727V

22. Large signal model for approximate hand caculation

23. Capacitors Of The MOSFET

25. Capacitors in Cutoff

26. Capacitors in Saturation

27. Capacitors in Triode

28. Small signal model

29. Typically: VDB, VSB are in such a way that there is a reversely biased pn junction.
Therefore: gbd ≈ gbs ≈ 0

30. In saturation:
But

31. Intrinsic DC voltage gain: gm/gds = gm*rds

32. In non-saturation region

33. Intrinsic gain
For large gain, use small ID or small over drive voltage, or in moderate to weak inversion.

34. High Frequency Figure of Merit wT
AC current source input to G
AC short S, D, B to gnd (i.e. constant voltages)
Measure AC drain current output
Calculate current gain
Find frequency at which current gain = 1.
Ignore rs and rd,  Cbs, Cbd, gds, gbs, gbd all have zero voltage drop and hence zero current
Vgs = Iin /jw(Cgs+Cgb+Cgd) ≈ Iin /jw(Cgs+Cgd)
Io = − (gm − jwCgd)Vgs ≈ − gm Iin /jw(Cgs+Cgd)
|Io/Iin| = |gm − jwCgd|/w(Cgs+Cgd) ≈ gm/w(Cgs+Cgd)

35. amplification
|Io/Iin|
attenuation wT
0 dB w

36. At wT, current gain =1
wT ≈ gm/(Cgs+Cgd)≈ gm/Cgs or

37. For fastest operation, use Vod near but before fT peak
For power efficiency, use Vod before fT corner

38. High Frequency Figures of Merit wmax
AC current source input to G
AC short S, B to gnd
Measure AC power into the gate
Assume complex conjugate load
Compute max power delivered by the transistor
Find maximum power gain
Find frequency at which power gain = 1.

40. gdo vs gm in short channel

41. gdo vs gm in short channel

43. Insights: gdo increases all the way with current density Iden
gm saturates when Iden larger than 100mA/mm
Velocity saturation, mobility degradation ---- short channel effects
Low gm/current efficiency
High linearity
For power efficiency and gm efficiency
Use moderate to low current density
Use small over drive voltage

44. To Av: (W/L), m, ID, l,
set VoQ at mid rail
For high speed:
Veff, m; L, Cgd, rg
For better linearity: Vds, Vdb, set VoQ at mid rail
Veff range: <~0.5V; or <~0.3V for efficiency
ID/W range: <100mA/mm; or <40mA/mm for efficiency

45. Intrinsic voltage gain of MOSFET
Sweep V1
Measure vgs
Intrinsic voltage gain = gm/go = Dvds/Dvgs for constant Id

46. Weak inversion
When VGS is reduced to Vth, the drain current does not go to zero
It does not follow square law
It does not follow exponential law
When VGS is markedly below Vth, the drain current becomes an exponential function of VGS.
Behaves very much like a diode

47. A model from weak to strong inv

48. In strong inversion
In strong inversion, n is about 1

49. In weak inversion

50. In weak inversion If vt = 25mV, n=2, gm/ID = 20 n=1.5, gm/ID = 27

51. ID vs VGS
Exponential model
Square law model
simulation

52. ID/(W/L) vs VG is sensitive to VBS

53. gm/ID vs VG is also sensitive to VBS

54. But gm/ID vs ID/(W/L) has fixed shape

55. Related VDD insensitive circuits
Filanovsky, etc, “Mutual Compensation of Mobility and Threshold Voltage Temperature Effects with Applications in CMOS Circuits”.
G. Giustolisi “A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs”.
Ka Nang Leung “A CMOS Voltage Reference Based on Weighted VGS for CMOS Low-Dropout Linear Regulators”.
Bernhard Boser. “Analog Circuit Design with Submicron Transistors". IEEE SSCS Meeting, Santa Clara Valley, May 2005.

59. TSMC 0.18 um Process

60. TSMC 0.18 um Process

61. TSMC 0.18 um Process

62. TSMC 0.18 um Process

63. TSMC 0.18 um Process

64. TSMC 0.18 um Process