1. Critical Dimension Control and its Implications in IC Performance
Costas J. Spanos
FLCC, 10/23/06
11/8/2018

2. Critical Dimension in Perspective (Leff in particular)
Controls both leakage and saturation current
Depends on Litho, Etch, Implant, Diffusion, Annealing
Its components can be measured with limited precision:
CD SEM: 1-2nm
Ellipsometry: ~0.5nm
Electrical: ~0.2nm
Has “hierarchical” nature with different variation mechanisms
Wafer to wafer
Across wafer
Across field, in 100’s of mm distances
Feature to feature, due to pattern density, etc.
Line edge roughness in 10’s of nm distances
Industry strives to keep TOTAL variability under 10%. This means 3 sigma total of less than 1nm in the next couple years.
11/8/2018

3. Outline CD Control CD Modeling IC Performance Impact New Directions
11/8/2018

4. Some of the recent advances in CD Control come from added Process Visibility – PEB, for example
Transient heating and cooling
Uniformity Control
HAND OUT THE WAFER FOR THE AUDIENCE TO PASS AROUND
Wafers are built on standard silicon oxide coated substrates,
the module has a low enough profile (4.5mm) to allow for full cassette to cassette transport on most major tools. (if they ask about their particular equipment, OnWafer has a database of tested equipment and also we can supply the mousetrap wafer – go to appendix slide by pressing the arrow button, bottom right of screen)
The sensors are coated with an inert polyimid.
The module contains the logic and memory and is encapsulated in polycarbonate
The unit is limited by the battery life which delivers approximately 100 hours at 130 degrees
The wafer can be directly loaded into the wafer cassette
Courtesy OnWafer Technologies
11/8/2018

5. PEB Temp Control Using Wireless Metrology using multi-zone plate modeling and feedback
Before
After
Target = 120oC
2.700oC
0.175oC
16 plates, 120 ºC Target
Courtesy OnWafer Technologies
11/8/2018

6. Post Exposure bake Driven CDU Improvement
Courtesy OnWafer Technologies
11/8/2018

7. We can also monitor Plasma Etch Temperature…
Routine He
Reduced He
pre-etch
main
etch
de-chuck
over etch
Courtesy OnWafer Technologies
11/8/2018

8. Present Status of “Active” CD Control
Exposure
Etch
PA Bake
PEB
Poly Etch System
Photoresist Removal
Etch
Etch
Spin
Develop
PD Bake
HMDS
ADI
AEI
ELM
11/8/2018

9. On-wafer and in-line metrology in pattern transfer
I (x, y)
T (t, x, y)
V (t, x, y)
E (t, x, y) …
Exposure
T (t, x, y)
Etch
PA Bake
PEB
Poly Etch System
Photoresist Removal
Etch
Etch
Thin Film
Develop
Spin
OCD
OCD
PD Bake
HMDS
OCD
ELM
11/8/2018

10. CDU control has to incorporate many strategies
I (x, y)
Optimal Pattern Design
T (t, x, y)
V (t, x, y)
E (t, x, y)
FF/FB Control, chuck diagnostics
Exposure
T (t, x, y)
FF control
Etch
PA Bake
PEB
Poly Etch System
Photoresist Removal
Etch
Etch
Thin Film
FB/FF Control
Develop
Spin
OCD
FB Control
OCD
FB/FF Control
PD Bake
HMDS
OCD
Profile Inversion
FB Control
ELM
11/8/2018

11. Dynamic Profile V.S. CD – 9 factors
Joint TSMC, UCB, OnWafer Paper, SPIE 2004
Experiments
Various PEB plate parameters determine behavior in each segment. These parameters were varied and CD data was collected at the same time
Dynamic Profile V.S. CD – 9 factors
Overshoot mean
Overshoot range
Steady state mean
Steady state range
Steady state duration
Cooling mean
Cooling range
Heating rate mean
Heating rate range
9 thermal-related factors are extracted and linked to CD maps.
Regression analysis is performed to establish statistical significance.

12. Within Lot CDU Summary 4 PHP/ 4DEV Baseline Adjusted 2nd iteration
Joint TSMC, UCB, OnWafer Paper, SPIE 2004
Within Lot CDU Summary
4 PHP/ 4DEV
Wafer to Wafer
CD range 3.4nm
CD range =3.4nm
Baseline
20 Wafers
Across Wafer CDU =3.8nm
CD range 1.5nm
Adjusted
20 Wafers
CDU=3.5nm
CD range 1.0nm
2nd iteration
25 Wafers
CDU=3.5nm
Dramatic CDU improvement was achieved with TCM

13. Supervisory Control with Wireless Metrology
Example chip speed map
Across-wafer (AW) CD (gate-length) uniformity impacts IC performance
Large AW CDV large chip-to-chip performance variation
low yield
How to cope with increasing AW CD variation?
Employ design tricks, e.g., adaptive body biasing, which has limitations
Reduce AW CD variation during manufacturing is the most effective approach
11/8/2018

14. CD Uniformity Control Approach
Making each process step spatial uniform is prohibitively expensive
Our approach: manipulate PEB temperature spatial distribution of multi-zone bake plate (and die-to-die dose) to compensate for other systematic across-wafer CD variation sources
CDU Control Framework
-Currently I am focusing on tuning the PEB spatial distribution to compensate for upstream and downstream variability
11/8/2018

15. Multi-zone PEB Bake Plate6
Approximate schematic setup of multi-zone bake plate
Each zone is given an individual steady state target temperature, by adjusting an offset value
T=Ttarget-Offset+effect of other zones 3 5 1 7 2 4
Zone offset knobs
PEB Bake
Plate
11/8/2018

16. Develop Inspection (DI) CDU Control Methodology II
DI CD is a function of zone offsets
Temperature Offset Model
CD Offset Model
Seen as a constrained quadratic programming problem
Minimize
Subject to:
11/8/2018

17. Final Inspection (FI) CDU Control Methodology
Plasma etching induced AW CD bias (signature)
Across-wafer FI CD is function of zone offsets
Minimize:
Subject to:
11/8/2018

18. FI CDU Control Verification Experiment Setup
Focus on Pitch 250 L/S 1:1, plate B
Use two-week-average FICD and bias signatures to generate offsets
Verification experiment is done sequentially
PEB adjustment is checked first to ensure it is close to the model-predicted one
DICD is then checked to ensure its correct adjustment
FICD is finally checked
Plate B (PEB adjusted)
(Litho)
PEB verification
Measure
DICD
DICD verification
Chamber (Etch)
Measure
FICD
FICD verification
6 wfrs
Verification experiment setup
11/8/2018

19. Long Term Overall Improvement ~35% in recently completed experiment at AMD/SDC across-wafer sigma of 250 1:1 lines, using CDSEM
Before
After
Confirmation Wafers (done six months after calibration)
σ=1.36nm
m=141.9nm
σ=1.21nm
m=142.1nm
σ=1.26nm
m=141.7nm
σ=1.14nm
m=141.5nm
σ=1.41nm
m=141.4nm
σ=1.39nm
m=142.4nm
11/8/2018

20. Verification experiment results (before control vs. after control)
The key point in the FICDU control approach is that the DI CD distribution is intentionally adjusted to cancel the plasma etch bias signature in order to improve FI CDU. So the tuned DICD variation may actually get worsen. Look at the DI CDV and FICD V for the 6 wafers in the characterization experiment and verification, we can see the DICD uniformity got worsen and the FICD uniformity was improved.
DICD uniformity is sacrificed in order to optimize FICD uniformity
Qiaolin (Charlie) Zhang, on internship at AMD/ Spansion
11/8/2018

21. Data Mining for Yield Ramping (APC)
What is it: Exploit existing tool/wafer data for control optimization
Basic Idea:
Wafer Metrology alone has limited precision – enhance it by combining tool/process/wafer data using multivariate techniques
Identify basic operating fingerprints, and distinguish from fingerprints in “rogue” situations
Combine basic operating fingerprints to predictive models suitable for APC
Potential Payoff:
Faster, more disciplined yield ramp
Rational deployment of metrology and control resources
Leapfrog present metrology precision/accuracy limitations
11/8/2018

22. Example of Proposed Control Deployment
Generate
Corrections
Process A Model
Process B Model
Recipe Model
Maintenance
Control Decisions
(supervisor decides on feedback/feed-forward)
Model-based
Controller
Model-based
Controller
Incoming Wafer
Outgoing Wafer
Process A
Process B
Production Metrology
SPC & recipe
Filter
SPC & recipe
Filter
Physical Wafer Measurements
Model
Maintenance
Model Prediction of
Physical and Electrical Wafer parameters
Control Limits driving control alarms
Process Specifications
11/8/2018

23. Virtual Metrology Preview
11/8/2018

24. Outline CD Control CD Modeling IC Performance Impact New Directions
11/8/2018

25. Motivation μsys(x,y), σ2rand μ, σ2 , ρ(Δx, Δy) Monte Carlo simulation:
Canonical circuit
Manuf. statistics
μsys(x,y), σ2rand
(ρμm(Δx, Δy))
Manuf. statistics
μ, σ2
spatial correlation
, ρ(Δx, Δy)
delay
power
11/8/2018

26. Decomposition of Spatial CD Variation= +
Average Wafer
Scaled Mask Errors
Across-Field Variation + + +
Across-Wafer Variation
Die-to-Die Variation
“Random” Variation
J. Cain and C. Spanos, “Electrical linewidth metrology for systematic CD variation characterization and causal analysis,” Metrology, Inspection, and Process Control for Microlithography XVII, Proceedings of SPIE vol. 5038, pp , 2003.
11/8/2018

27. Spatial Correlation & Process Control
Calculation of spatial correlation, before and following decomposition of variance:
Large(mm)-scale spatial correlation is largely accounted for by systematic variation; smaller, (μm)-scale correlation may still have structure, focus of current work
11/8/2018

28. Outline CD Control CD Modeling IC Performance Impact New Directions
11/8/2018

29. Digital Circuit Design and Sizing
Digital Circuit Sizing Optimization Problem
Goal: size the gates in a combinational logic circuit
Minimize the effects of individual gate delay variations and spatial correlations on the overall circuit delay
Previous Work: Geometric Programming approach
Objective:
where: Di = nominal delay for gate i
k = a constant ~ 2
derived from Pelgrom’s Model with model parameter γ
Constraints: Fixed maximum total circuit area † ††
† S. Boyd, S.-J. Kim, D. Patil, and M. Horowitz , “A Heuristic Method for Statistical Digital Circuit Sizing ,” 31st SPIE International Symposium on Microlithography, February †† M. Pelgrom, A. Duinmaijer and A. Welbers, “Matching Properties of MOS Transistors,”, IEEE J. Solid-state Circuits, Vol.24, No. 5, pp , Oct
11/8/2018

30. Performance Analysis Limitations
32-bit Ladner-Fisher adder circuit is sized and analyzed
459 gates, 3214 paths from input to output gates
Monte Carlo analysis with 5000 samples
RC model for nominal delay and a delay variation only due to vth
Overall circuit delay statistics are
compared under two designs:
Nominal Design, σ =0.88
Statistical Design, σ =0.47
Limitations
gate delay variation depends only on Vth
Ignored spatial correlations between the gates
† S. Boyd, S.-J. Kim, D. Patil, and M. Horowitz , “A Heuristic Method for Statistical Digital Circuit Sizing ,” 31st SPIE International Symposium on Microlithography, February 2006.
11/8/2018

31. More Comprehensive Designs
Adding delay variation dependence on Leff in the objective function:
where:
Adding variation dependence on Leff and Spatial Correlation
where:
ρij ≡ spatial correlation between gate i and j with separation dij
Large scale model
XL characteristic correlation length
ρB characteristic correlation baseline
11/8/2018

32. Monte Carlo Analysis on Circuit Delay
32-bit Ladner-Fisher adder circuit is analyzed
Four types of Monte Carlo analysis are performed for each design
σ(D)~σ(Vth): gate delay variation results from σ(Vth)
σ(D)~σ(Vth)+sp.corr: gate delay variation results from σ(Vth) and spatial correlations exist between the gates
σ(D)~σ(Vth)+σ(Leff): gate delay variation results from both σ(Vth) and σ(Leff)
σ(D)~σ(Vth)+σ(Leff)+sp. corr: gate delay variation results from σ(Vth), σ(Leff) and spatial correlations exits between the gates
11/8/2018

33. Simulation Results (5000 Monte Carlo Samples)
a) Deterministic design objective
b) Minimize delay variations due to Vth
(4) σ(D) ~ σ(Vth)+σ(Leff) sp. corr.
(1) σ(D) ~ σ(Vth)
(2) σ(D) ~ σ(Vth)+sp.corr.
(3) σ(D) ~ σ(Vth)+σ(Leff)
(4) σ(D) ~ σ(Vth)+σ(Leff) sp. corr.
(1) σ(D) ~ σ(Vth)
(2) σ(D) ~ σ(Vth)+sp.corr.
(3) σ(D) ~ σ(Vth)+σ(Leff)
frequency
frequency
c) Min. delay var. due to Vth and Leff
d) Min. delay var. due to Vth, Leff and Spa. Corr.
delay
(4) σ(D) ~ σ(Vth)+σ(Leff) sp. corr.
(1) σ(D) ~ σ(Vth)
(2) σ(D) ~ σ(Vth)+sp.corr.
(3) σ(D) ~ σ(Vth)+σ(Leff)
(4) σ(D) ~ σ(Vth)+σ(Leff) sp. corr.
(1) σ(D) ~ σ(Vth)
(2) σ(D) ~ σ(Vth)+sp.corr.
(3) σ(D) ~ σ(Vth)+σ(Leff)
frequency
frequency
delay
delay
11/8/2018

34. Simulation Results
Focus on the last analysis which considers both delay variations due to Vth and Leff, and spatial correlations
a) Deterministic design
σ(D) = 3.02, yield = 63.42%
frequency
b) Minimize delay variations due to Vth
σ(D) = 1.96, yield = 92.06%
c) Min. delay var. due to Vth and Leff
σ(D) = 1.52, yield = 96.62%
d) Min. delay var. due to Vth, Leff and spatial correlation
σ(D) = 1.36, yield = 98.22%
delay
11/8/2018

35. Outline CD Control CD Modeling IC Performance Impact New Directions
11/8/2018

36. Matching Properties of MOSFETs†
Matching Properties of MOSFETs x
(x12,y12)
(x1,y1)
(x2,y2) W L Dx
Average value of the parameter over any area is given by the integral of P(x,y) over this area.
Actual mismatch is given by the difference of two integrals
This integral can be interpreted as the convolution of a geometry function with the “mismatch source” function P(x,y)
† M. Pelgrom, A. Duinmaijer and A. Welbers, “Matching Properties of MOS Transistors,”, IEEE J. Solid-state Circuits, Vol.24, No. 5, pp , Oct
11/8/2018

37. First Source of Variation – White Noise
The events have a correlation distance much smaller than the transistor dimensions.
In Fourier domain it is a constant value for all spatial frequencies
The assumption of short correlation distance implies that no relation exists between matching and the spacing D between two transistors.
But what if W and L are also variable?
11/8/2018

38. Additional Sources of Variation are Deterministic
Systematic error from across wafer variations
Systematic error from within field variations
Scanner optics / mechanics
Mask errors
Pattern densities (in Litho, Etch, CMP, Anneal, etc.)
And, of course, LER… P
Wafer diameter
+ ?
How do we deal with the complexity of the deterministic functions?
11/8/2018

39. Device Model and Yield under LER
Source
Drain
Li-1
Li+1 Li
11/8/2018

40. FinFET LER h t A B C
Body = + L
Gate
11/8/2018

41. FinFET LER A B C C h B t A h L
11/8/2018

42. FinFET LER Issues Hot carrier reliability
Mobility degradation due to surface scattering
Si FinFET vs. TFT
Ioff and Ion variations due to LER
Orientation effects
Poly-Si vs. sc-Si
TFT vs. bulk
11/8/2018

43. Transfer of LER
Transfer of LER from resist film onto underlying film is a multi-step process
Furthermore, the junction edges of tip and halo implants is redefine the LER underneath the etched gate stack
Schematic of a typical gate stack
Resist
Poly-Si
Gate Dielectric
Substrate
Hard Mask
BARC
11/8/2018

44. Outline CD Control CD Modeling IC Performance Impact New Directions
11/8/2018

45. In Summary
CD (and many other, equally critical elements) vary in a complex manner
We are observability- and controllability-limited
Major efforts are under way to
Enhance the metrology capability
Reform and expand the models of variability
Incorporate variability modeling into DFM tool
We are bringing in enhanced CD metrology capability by the donation of the Timbre/TEL ODP tool
11/8/2018