1. A Review of Processor Design Flow
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cpeg323\Topics1b.ppt

2. How to design a CPU ? Component-level design
Instruction-set architecture (ISA) design
Function-level (RTL) design
Component-level design
Gate-level/switch-level design
Circuit-level design
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cpeg323\Topics1b.ppt

3. Design Method Gate Level: full CAD
Register Level: CAD + heuristics/intuition
ISA Level: mainly heuristic process
with simulation validation
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cpeg323\Topics1b.ppt

4. Processor Architecture
Instruction Set
Architecture
Design
(Microarchitecture
Design-I)
System-Level
RTL Level Design
Design II)
Compiler
Code
Optimizer
Hardware
Switch
Level
Circuit
design
ISA
Simulator
System Level
RTL
Arch./Compiler
Design Toolset
Processor Architecture
Design Flow
Diagram
HDL (VHDL or Verilog)
Generator
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cpeg323\Topics1b.ppt

5. Design Levels of Abstraction
cpu
cpu
eax
Iunit
mov eax, [edi]
cmp eax, 4
jne label10
Micro architecture F D E W
Architecture
ebx
Dunit
ecx
edx
Bunit
RenIfsSetWb2H :=
vOR3(RenCoverUpdtIFMWb2H,
vAND2(RenCrab_Data_Hi_Cx5B[31],
RenCrabIfsWrEnCx5H), vAND2(RenIfsValidWb3H,
vNOT(RenCrabIfsWrEnCx5H)))
Logic
Circuit
Layout
Concrete
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cpeg323\Topics1b.ppt

6. Design Levels and Component Types
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cpeg323\Topics1b.ppt

7. Classical ISA Level Design Method
Select a prototype structure A
Modify A to accommodate:
new performance demand and new technology
Evaluation (ISA simulation)
Repeating until satisfaction
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cpeg323\Topics1b.ppt

8. Overall Simulation Strategy
Instruction level simulator: this is used for performance evaluation at the instruction set level as well as for more detailed modeling, e.g. the pipeline and memory system. This level is also used to generate test vectors employed in lower-level simulators.
System level simulation: this simulator models the details of the system environment including such things as interrupts and memory management.
(Virtual machine level ..)
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cpeg323\Topics1b.ppt

9. Overall Simulation Strategy
(Con’d)
3. RTL level: this simulator models are RTL description of the design
Switch level with delays: used to simulate the design mostly in components; test vectors are generated from the RTL level.
5. Circuit simulation: it is used for detailed modeling of the critical paths as well as for verification of circuits under variations in temperature, power supply, etc.
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cpeg323\Topics1b.ppt

10. Performance of Simulators
# of cycles simulated per second on a host machine
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cpeg323\Topics1b.ppt

11. Instruction Set Architecture Simulation
Runtime
statistics
(frequencies,
cycle counts, etc.)
Object
file
Execution
-driven
simulator
Profile
information
Traces
(e.g. memory accesses
branch trace, etc.)
Architecture
Models
Trace-driven
simulator
(cache simulator
branch prediction
simulator, etc.)
Statistics
(e.g. cache behavior,
branch behavior, etc.)
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cpeg323\Topics1b.ppt

12. Performance Study by Simulation
Develop performance model that is:
Flexible
Parameterized (via knobs)
95% clock accurate compared to RTL
Significantly smaller than RTL
Models consist of two parts:
Instruction-set simulator -> executes benchmark
Pipeline simulator -> “accountant” for clock cycles
Run benchmarks, update microarchitecture accordingly
Cycle of: code -> simulate -> characterize -> tune
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cpeg323\Topics1b.ppt