1. Assignment 4 – (a)
Consider a symmetric MP with two processors and a cache invalidate write-back cache. Each block corresponds to two words in memory. The initial state of memory and the caches are shown in the next slide. Complete the state of each of the two caches after each of the references indicated at the bottom left of each subsequent slide. Assume that new entries coming to a cache replace the entry with a state of invalid (I) that has the lowest tag number.
You need to show the entire cache state in each slide, not just the change!
You need to turn in all the slides (in hardcopy).

2. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 I B0 S B1 S B1 M B2 M B2 I B3 I I B3
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
Initial State

3. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 B0 B1 B1 B2 B2 B3 B3
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
After reference 1:
P0: read 128

4. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 B0 B1 B1 B2 B2 B3 B3
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
After reference 2:
P1: read 132

5. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 B0 B1 B1 B2 B2 B3 B3
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
After reference 3:
P0: write 128  20 15

6. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 B0 B1 B1 B2 B2 B3 B3
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
After reference 4:
P1: read 128

7. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 B0 B1 B1 B2 B2 B3 B3
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
After reference 5:
P0: reads 110

8. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 B0 B1 B1 B2 B2 B3 B3
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
After reference 6:
P1: reads 110

9. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 B0 B1 B1 B2 B2 B3 B3
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
Memory after cache
write-back:
128