1. Day 6: September 11, 2013 Restoration
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 6: September 11, 2013
Restoration
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2. Today How do we make sure logic is robust
Can assemble into any (feed forward) graph
Can tolerate voltage drops and noise
….while maintaining digital abstraction
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3. Outline Two problems Cascade failure Restoration Transfer Curves
Noise Margins
Non-linear
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4. Two Problems Output not go to rail Signals may be perturbed by noise
Stops short of Vdd or Gnd
Signals may be perturbed by noise
Vx = Videal ± Vnoise
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5. Wire Resistance Last Wednesday: Rwire=10Ω
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6. Wire Resistance 1000 mm long wire? 1 cm long wire?
Length of integrated circuit chip side?
(we often call an IC chip a “die”)
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7. Die Sizes Processor Die Size Transistor Count Process
Core 2 Extreme X mm² 291 Mio. 65 nm
Core 2 Duo E mm² 291 Mio. 65 nm
Core 2 Duo E mm² 291 Mio. 65 nm
Core 2 Duo E mm² 167 Mio. 65 nm
Core 2 Duo E mm² 167 Mio. 65 nm
Pentium D mm² 376 Mio. 65 nm
Athlon 64 FX mm² 227 Mio. 90 nm
Athlon mm² 154 Mio. 90 nm
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8. Implications
What does the circuit really look like for an inverter in the middle of the chip?
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9. Implications
What does the circuit really look like for an inverter in the middle of the chip?
Rwire
Rrest_of_chip
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10. Rrest_of_chip
IR-Drop
Since interconnect is resistive and gates pull current off the supply interconnect
The Vdd seen by a gate is lower than the supply Voltage by
Vdrop=Isupply x Rdistribute
Two gates in different locations
See different Rdistribute
Therefore, see different Vdrop
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11. Output not go to Rail CMOS, capacitive load  no problem
CMOS, resistive load  voltage divider
Due to IR drop, “rails” for two communicating gates may not match
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12. Two Problems Output not go to rail Signals may be perturbed by noise
Is this tolerable?
Signals may be perturbed by noise
Voltage seen at input to a gate may not lower/higher than input voltage
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13. Noise Sources?
What did we see in lab when zoomed in on signal transition?
Signal coupling
Crosstalk
Leakage
Ionizing particles
IR-drop in signal wiring
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14. Signals will be degraded
Output not go to rail
Is this tolerable?
Signals may be perturbed by noise
Voltage seen at input to a gate may not lower/higher than input voltage
What happens to degraded signals?
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15. Preclass
All 1’s  logical output?
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16. Preclass 1.0 inputs, gate: o=1-AB  output voltage?
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17. Preclass 0.95 inputs, gate: o=1-AB  output voltage?
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18. Degradation Cannot have signal degrade across gates
Want to be able to cascade arbitrary set of gates
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19. Gate Creed Gates should leave the signal “better” than they found it
“better”  closer to the rails
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20. Restoration Discipline
Define legal inputs
Gate works if Vin “close enough” to the rail
Restoration
Gate produces Vout “closer to rail”
This tolerates some drop between one gate and text (between out and in)
Call this our “Noise Margin”
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21. Noise Margin Voh – output high Vol – output low Vih – input high
Vil – input low
NMh = Voh-Vih
NMl = Vil-Vol
One mechanism,
addresses numerous
noise sources.
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22. Restoration Discipline (getting precise)
Define legal inputs
Gate works if Vin “close enough” to the rail
Vin > Vih or Vin < Vil
Restoration
Gate produces Vout “closer to rail”
Vout < Vol or Vout > Voh
Note: don’t just say Vin>Vih  Vout>Voh
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23. Transfer Function
What gate is this?
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24. Restoring Transfer Function
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25. Decomposing What is gain? Where is there gain?
|DVout/Dvin| > 1
Where is there gain?
Where is there not gain?
Dividing point?
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26. Restoring Transfer Function
Vil, Vih = slope -1 points
Voh =f(Vil)
Vol=f(Vih)
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27. Restoring Transfer Function
Vil, Vih = slope -1 points
Voh =f(Vil)
Vol=f(Vih)
Closer to rail than Vil, Vih
Not make much difference on Vout
Making Vil lower would reduce NM = Vil-Vol
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28. Controlling Value Consider a nor2 gate
If want one input to control the output
What value should the other input be?
We call this input the non-controlling input since it does not determine the output
What should the non-controlling input value be for a nand2 gate?
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29. Restoring Transfer Function
For multi-input functions,
should be worst case.
i.e.
hold non-controlling inputs
at Vil, Vih respectively.
(relate preclass exercise)
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30. Ideal Transfer Function
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31. Linear Transfer Function?
O=Vdd-A
Noise Margin?
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32. Linear Transfer Function?
Consider two in a row (buffer)
O1=Vdd-A
What is transfer function to buffer output O2?
O2=(Vdd-O1) = Vdd-(Vdd-A)=A
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33. Linear Transfer Function?
For buffer: O2=A
Consider chain of buffers
What happens if A drops a bit between each buffer?
Ai+1 = Ai-Δ
Conclude: Linear transfer functions
do not provide restoration.
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34. Non-linearity Need non-linearity in transfer function
Could not have built restoring gates with
R, L, C circuit
Linear elements
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35. Transistor Non-Linearity
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36. All Gates If we hope to assemble design from collection of gates,
Voltage levels must be consistent and supported across all gates
Must adhere to a Vil, Vih, Vol, Voh that is valid across entire gate set
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37. Big Idea Need robust logic Restoration and noise margins
Can assemble into any (feed forward) graph
Can tolerate loss and noise
….while maintaining digital abstraction
Restoration and noise margins
Every gate makes signal “better”
Design level of noise tolerance
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38. Admin HW2 due Thursday (tomorrow) Friday in Ketterer Monday back here
Noise margin problem
Friday in Ketterer
Read through HW3
Transfer library/schematics to eniac
Be ready to run electric and spice on linux
CETS machines
<or> own laptop that you bring with you
Monday back here
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